Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 5262687 | Decoder circuit with bypass circuitry and reduced input capacitance for greater speed An address detection circuit is described having a node A which is precharged to the voltage of a power supply and then discharged down to ground by a strobe signal if an address match occurs. An address match is detected when a nonconventional CMOS inver... | 11/16/1993 |
| 5262994 | Semiconductor memory with a multiplexer for selecting an output for a redundant memory access An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column... | 11/16/1993 |
| 5258666 | CMOS clocked logic decoder The present semiconductor logic circuit includes a first-stage logic circuit section comprising of a first precharging transistor, a first grounding transistor, and a first logic element and a second-stage logic circuit section comprising of a second prec... | 11/02/1993 |
| 5257229 | Column redundancy architecture for a read/write memory An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column... | 10/26/1993 |
| 5250857 | Dynamic logic circuit with reduced operating current In a dynamic logic circuit, an X decoder and a Y decoder receive a more significant bit portion and a less significant bit portion of an internal address generated by a sequencer, respectively. A precharge signal supplied to the X decoder is generated whe... | 10/05/1993 |
| 5245583 | Integrated circuit memory with decoded address sustain circuitry for multiplexed address architecture and method An integrated circuit memory device is provided which includes a memory array including multiple memory cores, each core including a two-dimensional (x,y) array of memory cells, the memory array further including a plurality of x-lines and a plurality of ... | 09/14/1993 |
| 5233240 | Semiconductor decoding device comprising an MOS FET for discharging an output terminal For implementation typically as an IC, a semiconductor decoding device comprises an additional MOS FET (26) of a first conductivity type between ground and output terminals, each (12) of which is connected to a power supply terminal (19) through a load MO... | 08/03/1993 |
| 5223834 | Timing control for precharged circuit A timing control for precharged digital circuits to avoid spurious error appearing at the output due to the slow pull-down of the precharged node after precharging. A NAND gate is used to delay the precharged node siganl transmitting to the output stage u... | 06/29/1993 |
| 5224071 | Addressable memory unit having an improved unit selection circuit An addressable memory unit has address input buffer circuits which output a pair of output connections on which, in read or write mode, two signals which are complementary to one another are present but which may also adopt equal values in such a manner a... | 06/29/1993 |
| 5223752 | Level conversion circuit for converting ECL-level signals into mos-level signals and address signal decoding system having the level conversion circuit A level conversion circuit includes first to nth circuits, each having an input terminal and first to nth output terminals where n is an integer, and first to nth signal lines coupled to the first to nth circuits. Each of the first to nth circuits compris... | 06/29/1993 |
| 5202592 | Programmable logic device In selectors 210 -213 two pull-up switching elements 40-403, 420 -423, the elements being connected in series to each other in each selector, are additionally provided instead of a don't care-setting ... | 04/13/1993 |
| 5197028 | Semiconductor memory device with dual reference elements The invention involves a semiconductor memory device having a memory cell with a drain, a gate and a source. The gate of the memory cell is supplied with a first potential for reading a memory cell data. A first reference line is connected to the drain of... | 03/23/1993 |
| 5159215 | Decoder circuit A decoder circuit comprises a P type substrate in which an N well is formed, a plurality of P channel word line drive transistors each having a gate supplied with a signal having a level corresponding to an address signal and a source-drain connected betw... | 10/27/1992 |
| 5157283 | Tree decoder having two bit partitioning Disclosed is a decoder circuit designed to reduce the number of transistor elements and to increase the speed of operation. The decoder includes a plurality of output selectors for respectively drawing out different decoded output signal lines in group ha... | 10/20/1992 |
| 5155398 | Control circuit for high power switching transistor A pair of series connected high power MOS transistors, each including a plurality of transistors formed on a single chip in parallel, with a control circuit including a pair of logic gates connected to different points of the control electrodes of the pow... | 10/13/1992 |
| 5138197 | Address decoder array composed of CMOS A NAND-system address decoder is configured by arranging the P-channel- and N-channel logical blocks in parallel and input wires to which address signals are supplied is extendedy formed in the direction in which the above logical blocks are arranged. And... | 08/11/1992 |
| 5109167 | PNP word line driver The present invention is directed to a decoder implemented with metal oxide semiconductor (MOS) field effect transistors (FETs) and a bipolar transistor in a collector-follower configuration. In one embodiment, NPN transistors perform decoding, FETs are u... | 04/28/1992 |
| 5103113 | Driving circuit for providing a voltage boasted over the power supply voltage source as a driving signal A driving circuit for providing a predetermined voltage as a driving signal to a respective word line in a dynamic random access memory in a short time. The driving circuit includes an operation signal supply circuit portion for providing an operation sig... | 04/07/1992 |
| 5059825 | Nand gate circuit A NAND gate circuit which can be used for a decoder circuit, includes a high potential voltage source (Vcc), an output terminal (VOUT), and a load element (T1) connected between the high potential electric voltage source (... | 10/22/1991 |
| 5055717 | Data selector circuit and method of selecting format of data output from plural registers Data selector circuit including a plurality of data registers connected in parallel via corresponding output buffers to a plurality of output drivers, wherein a decoder and selector portion is interposed between the output buffers and the output drivers f... | 10/08/1991 |
| 5045720 | Method for selecting a spare column and a circuit thereof There is provided a spare column selection circuit comprising a line switching pair arranged between a spare input/output line pair connected to a spare bit line and a normal input/output line pair connected to a normal bit line pair. The line switching p... | 09/03/1991 |
| 5039882 | Address decoder circuit for non-volatile memory An address decoder circuit adapted for enabling electrical erasure in a non-volatile memory without the necessity of numerically increasing the component elements, wherein the direction of application (polarity) of a supply voltage during an erasing opera... | 08/13/1991 |
| 5022010 | Word decoder for a memory array A word decoder for a memory array includes a decode NOR/OR circuit 52 coupled to an output driver circuit 54. Decode NOR/OR circuit 52 includes a plurality of input signals IN1, IN2, IN3 connected to respective input n-channel field effect transistor (NEF... | 06/04/1991 |
| 4967399 | Erasable and programmable read-only memory system Am EPROM system comprising a memory cell array formed of a matrix of non-volatile semiconductor memory cells, each having a control gate and a floating gate, and storing electric charges on the floating gate, and a word line drive circuit driving respecti... | 10/30/1990 |
| 4962327 | Decoder circuit having selective transfer circuit for decoded output signal A decoder circuit comprises a plurality of signal conductors, first potential setting units for setting a potential of the signal conductors to a first potential, second potential setting units for maintaining a potential of one signal conductor at the fi... | 10/09/1990 |
| 4947059 | Method of dividing an input-output line by decoding There is provided apparatus for dividing an input/output line coupled to a sense amplifier which is driven by the status of a bit line pair, the apparatus comprising a sub input/output line connected to the bit line pair through corresponding first MOS tr... | 08/07/1990 |
| 4922134 | Testable redundancy decoder of an integrated semiconductor memory A redundancy decoder of an integrated semiconductor memory having a plurality of decoder stages containing a switching transistor and a separable connection having respective conditions in which the separable connection is severed and intact, as well as a... | 05/01/1990 |
| 4902919 | Inverting latching bootstrap driver with Vdd *2 booting An inverting latching bootstrap driver is used to drive a load where the input to the driver may change during the driving phase. The input to the driver circuit is controlled by a precharge/discharge type decoder. The bootstrap driver samples the input d... | 02/20/1990 |
| 4899315 | Low-power, noise-resistant read-only memory A low-power, noise-resistant, read-only memory (10) is comprised of a plurality of array sections (14), each section (14) having a plurality of cell locations (70-86) arranged in rows (98) and columns (88-96). Each column (88-96) is provided with a virtua... | 02/06/1990 |
| 4896302 | Semiconductor memory device having common driver circuits for plural memory cell arrays In a semiconductor memory device, a decoder circuit is located between first and second memory cell arrays. A sequence of driver circuits in the decoder circuit is provided as driver circuits common to the first and second memory cell arrays. The output t... | 01/23/1990 |
| 4887239 | One-time programmable data security system for programmable logic device A data security fuse system is disclosed for allowing one-time programmability of protected data cells in a reprogrammable logic device, which may determine, for example, the logic architecture of the device. The system includes a fuse enable circuit whic... | 12/12/1989 |
| 4881199 | Read circuit for reading the state of memory cells A read circuit is disclosed for integrated circuits of the logic circuit type, comprising a memory consisting of a matrix of memory cells, the reading of which is done by the detection of a current variation or voltage variation, the memory cells being ea... | 11/14/1989 |
| 4878195 | Instruction sequencer for network structure microprocessor The invention concerns an instructions sequencer for microprocessor wherein the sequencer presents an architecture, a circuit conception and a presents that improves the compacity and facilitates conception and adaptation operations to different instructi... | 10/31/1989 |
| 4866305 | Multiple-input multiple-output decoding circuit A decoding circuit comprises an m row by n column matrix arrangement of transmission gates, wherein an output terminal of one of two mutually adjacent transmission gates in each column of the matrix arrangement is connected to an input terminal of the oth... | 09/12/1989 |
| 4857772 | BIPMOS decoder circuit A decoder incorporates the advantageous features of both bipolar and BICMOS decoding circuits through the use of BIPMOS technology. PMOS gating transistors are used to control the operation of bipolar output transistors. It is only necessary to operate th... | 08/15/1989 |
| 4855621 | Multi-stage, integrated decoder device having redundancy test enable A multi-stage, integrated decoder device includes a special function which facilitates the simultaneous activation of a plurality or as many as all of its outputs while gating out a pre-selectible output. When used as bit line decoder, it is thus possible... | 08/08/1989 |
| 4833348 | Decoder unit with clamp transistor preventing excessive voltages For elimination of mis-decoding operation, there is disclosed a decoder unit comprising a logic gate having input nodes respectively supplied with data bits of an input signal and carried out a logical operation to decide a logic level at an output node t... | 05/23/1989 |
| 4831284 | Two level differential current switch MESFET logic A GaAs differential current switch (DCS) logic family is disclosed. Two cross-coupled, push-pull output buffer stages are coupled to the DCS logic circuit to increase the gain and to improve noise margins. The circuit is compatible with other GaAs logic f... | 05/16/1989 |
| 4823317 | EEPROM programming switch An EEPROM programming switch includes a first enhancement mode field effect transistor interconnected between a word line and a programming voltage potential, and a second enhancement mode field effect transistor connected between a charge pump node and t... | 04/18/1989 |
| 4817033 | Signal detecting circuit A signal detecting circuit for detecting signals from a signal output circuit having a predetermined number of output terminals of which only one output terminal is to be normally selected during each recurrent cycle of operation, comprising the combinati... | 03/28/1989 |
