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| Number | Title | Issue Date |
| 8138797 | Integrated circuits with asymmetric pass transistors Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Sele... | 03/20/2012 |
| 8093923 | Semiconductor device An RESURF region is formed so as to surround a high-potential logic region with an isolation region interposed therebetween, in which a sense resistance and a first logic circuit which are applied with a high potential are formed in high-potential logic region. On t... | 01/10/2012 |
| 7902880 | Transitioning digital integrated circuit from standby mode to active mode via backgate charge transfer Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more ... | 03/08/2011 |
| 7342422 | Semiconductor device having super junction structure and method for manufacturing the same A semiconductor device includes: a cell region; a terminal region; a lower semiconductor layer; a intermediate semiconductor layer on the lower semiconductor layer including a super junction structure; a terminal upper semiconductor layer on the intermediate semicon... | 03/11/2008 |
| 7334206 | Cell builder for different layer stacks A library cell, a method and/or a system for adding the cell to a circuit is disclosed. The method generally comprises a first step for generating a final layout of the cell having an area of interest in at least one upper layer within a first layer stack used for t... | 02/19/2008 |
| 7254082 | Semiconductor device When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from tu... | 08/07/2007 |
| 7233166 | Bus state keepers Bus state keepers to maintain a steady state of an inactive bus to conserve power. In one embodiment of the invention, the bus state keepers include a plurality of multiplexers and a plurality of flip flops. The plurality of flip flops to store a state of a bus in r... | 06/19/2007 |
| 7231624 | Method, system, and article of manufacture for implementing metal-fill with power or ground connection Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connectio... | 06/12/2007 |
| 7193442 | USB 1.1 for USB OTG implementation This invention enables a USB 1.1 device and a USB 1.1 host to communicate seamlessly with a USB OTG device. The invention complies with both USB 1.1 and OTG specifications. The invention includes the USB 1.1 host, USB 1.1 device and mixed signal circuits to implemen... | 03/20/2007 |
| 7164294 | Method for forming programmable logic arrays using vertical gate transistors One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each including a plurality of logic cells interconnected to implement a logical fu... | 01/16/2007 |
| 7095063 | Multiple supply gate array backfill structure A multiple supply gate array structure facilitated by the provision of a shared n-well and an isolated n-well is described. The gate array structure allows implementation of a single voltage circuit or a multiple voltage circuit. In addition, the gate array structur... | 08/22/2006 |
| 7078936 | Coupling of signals between adjacent functional blocks in an integrated circuit chip A modifiable circuit for coupling at least two adjacent logic blocks in an integrated circuit chip is disclosed. The chip includes a plurality of metal layers and first and second power supply potentials. The circuit comprises a first and second metal interconnect s... | 07/18/2006 |
| 7078932 | Programmable logic device with reduced power consumption The present invention provides a programmable logic device with reduced power consumption comprising, a first set of data storage elements, at least a first power supply connected to the said first set of data storage elements, a second set of substantially identica... | 07/18/2006 |
| 7028282 | Integrated circuit with layout matched high speed lines A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between lon... | 04/11/2006 |
| 7023751 | Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage The required refresh rate of a DRAM is reduced by biasing active digit lines to a slight positive voltage to reduce the sub threshold current leakage of access transistors in memory cells that are not being accessed. The slight positive voltage is provided by a volt... | 04/04/2006 |
| 7018889 | Latch-up prevention for memory cells An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source o... | 03/28/2006 |
| 7020016 | Random access memory cell and method for fabricating same A data value is stored in a random access memory cell by driving the bit lines of the cell to complementary values representative of the value. The word line for the cell is driven to make a cell selection and cause the data value to be loaded into the cell from the... | 03/28/2006 |
| 6960932 | Apparatus and method to correct a reference voltage An apparatus and method thereof to correct a reference voltage, Vref, include a first digital device and a second digital device to input/output digital data via a bus, an adjustable resistor providing a main supply voltage VDD, a fixed resistor, wherein the adjusta... | 11/01/2005 |
| 6958519 | Methods of forming field effect transistors and field effect transistor circuitry Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and conn... | 10/25/2005 |
| 6949957 | Command user interface with programmable decoder A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropri... | 09/27/2005 |
| 6894532 | Programmable logic arrays with ultra thin body transistors Structures and methods for programmable logic arrays are provided. In one embodiment, the programmable logic array includes a first logic plane and a second logic plane. The first logic plane receives a number of input signals. The first logic plane has a plurality ... | 05/17/2005 |
| 6876226 | Integrated digital circuit The invention relates to an integrated digital circuit comprising a logic circuit portion which takes one of at least two different logic states in accordance with provided control signals. In order to minimize the power consumption and to enable a fast start up of ... | 04/05/2005 |
| 6810512 | Integrated circuit with layout matched high speed lines A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between lon... | 10/26/2004 |
| 6804305 | Wide common mode range differential receiver Disclosed is a wide common mode range differential receiver comprising an input stage adapted to receive an input signal and its complement with wide common mode and output said signals as current signals; a plurality of self-cascode biasing stages adapted to receiv... | 10/12/2004 |
| 6794904 | Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground lin... | 09/21/2004 |
| 6774671 | Multi-purpose transistor array The addition of an array of transistors through areas of the circuit where active devices normally don't exist, such as under routing channels. By connecting this array of transistors such that the gates are tied to one power supply and the sources and drains to ano... | 08/10/2004 |
| 6690206 | Semiconductor integrated circuit device A pass-transistor logic circuit configuration that can form a high-speed chip in a small area with short wire length. In a selector circuit PMOS and NMOS transistors with different gate signals but with the same drain outputs are arranged, respectively, s... | 02/10/2004 |
| 6683476 | Contact ring architecture An integrated circuit with a VDDio bus line disposed on a first layer of the integrated circuit. The VDDio bus line is disposed along a length, and has a first width transverse to the length. A VSSio bus line is dispose on a second layer of the integrated... | 01/27/2004 |
| 6636075 | Semiconductor integrated circuit and its fabrication method An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type... | 10/21/2003 |
| 6600341 | Integrated circuit and associated design method using spare gate islands An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell por... | 07/29/2003 |
| 6597200 | Circuit arrangement for scalable output drivers The invention provides a circuit arrangement for scalable output drivers, symmetrically arranged driver transistor groups being provided which each have transistor pairs having the same transistor line width. If there are m different driver transistor gro... | 07/22/2003 |
| 6571380 | Integrated circuit with layout matched high speed lines A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed ... | 05/27/2003 |
| 6530068 | Device modeling and characterization structure with multiplexed pads A multiplexed transistor characterization and modeling structure for testing a plurality of transistors, The characterization and modeling structure comprises a common substrate pad, a common source pad, a plurality of drain pads, and a plurality of gate ... | 03/04/2003 |
| 6529035 | Arrangement for improving the ESD protection in a CMOS buffer An arrangement for improving the ESD protection in a CMOS buffer includes a plurality of PMOS transistors (31 to 37) and a plurality of NMOS transistors (41-47) which are connected in series with the PMOS transistors and have a finger width WN ... | 03/04/2003 |
| 6515511 | Semiconductor integrated circuit and semiconductor integrated circuit device A semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate. Each of the basic cells includes a wire selection portion and a logic gate portion. The log... | 02/04/2003 |
| 6515510 | Programmable logic array with vertical transistors A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and ... | 02/04/2003 |
| 6496040 | Trading off gate delay versus leakage current using device stack effect A stack device is provided to obtain a stack effect. The stack device includes at least first and second active components. The first and second active components have first and second device widths, respectively. The first and second device widths are th... | 12/17/2002 |
| 6496034 | Programmable logic arrays with ultra thin body transistors Structures and methods for programmable logic arrays are provided. In one embodiment, the programmable logic array includes a first logic plane and a second logic plane. The first logic plane receives a number of input signals. The first logic plane has a... | 12/17/2002 |
| 6480032 | Gate array architecture Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes at least one base site, the at least one base site being three tracks wide and including four N-ty... | 11/12/2002 |
| 6437389 | Vertical gate transistors in pass transistor programmable logic arrays Systems and methods are provided for vertical gate transistors in static pass transistor programmable logic arrays. The vertical gate transistors have multiple vertical gates which are edge defined such that only a single transistor is required for multip... | 08/20/2002 |
