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| Number | Title | Issue Date |
| 8390330 | Base cell for implementing an engineering change order (ECO) A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on th... | 03/05/2013 |
| 8384439 | Semiconductor devices and methods of fabricating the same Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may be a complementary device including a p-type oxide TFT and an n-type oxide TFT. The semiconductor device may be a logic device such as an inverter,... | 02/26/2013 |
| 8378715 | Method to construct systems A method to construct first and second configurable systems including: providing a first configurable system including a first die and a second die, where the first die is diced from a first wafer and the second die is diced from a second wafer and the first die is ... | 02/19/2013 |
| 8373441 | Orienting voltage translators in input/output buffers Described embodiments provide for a semiconductor device comprising a core and one or more input/output (I/O) buffers surrounding the core. The I/O buffers are adapted to transfer signals associated with core circuitry of the core. The I/O buffers comprise I/O cells... | 02/12/2013 |
| 8354861 | Magnetoresistive element, logic gate and method of operating logic gate A logic gate has a magnetoresistive element, a magnetization state control unit and an output unit. The magnetoresistive element has a laminated structure having N (N is an integer not smaller than 3) magnetic layers and N−1 nonmagnetic layers that are alternately... | 01/15/2013 |
| RE43912 | Semiconductor integrated circuit A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of g... | 01/08/2013 |
| 8324937 | Methods for differential pair conductor routing in a logic circuit Methods for differential pair conductor routing in a logic circuit. One embodiment includes a method for differential pair conductor routing in a logic circuit, by routing conductors of a first line width to obtain a first routing for a first logic library, wherein ... | 12/04/2012 |
| 8299818 | Semiconductor integrated circuit A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply ... | 10/30/2012 |
| 8289051 | Input/output core design and method of manufacture therefor One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side paral... | 10/16/2012 |
| 8237470 | Universal IO unit, associated apparatus and method A universal IO unit applied to a chip or an integrated circuit is provided. The universal IO unit includes a power pad and a plurality of signal pads for providing different functions. According to functional requirements of the universal IO unit, the pad power is s... | 08/07/2012 |
| 8138796 | Serial configuration interface A serial configuration interface (SCI) used to configure a device is disclosed. A device that support SCI includes a first connector configured to receive a first signal and a second connector configured to receive a second signal. In a configuration mode, the first... | 03/20/2012 |
| 8089301 | Inverter and logic device comprising the same The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transist... | 01/03/2012 |
| 8072243 | Semiconductor device with transistors having substantial the same characteristic variations A semiconductor device is provided. The semiconductor device includes a first circuit provided between a power source voltage line and a ground line, including at least two first MOS transistors coupled in parallel and a second circuit, which is provided between the... | 12/06/2011 |
| 8004315 | Process for making and designing an IC with pattern controlled layout regions The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient... | 08/23/2011 |
| 7969199 | Pattern controlled IC layout The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient... | 06/28/2011 |
| 7965107 | Base cell for engineering change order (ECO) implementation A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pa... | 06/21/2011 |
| 7944243 | Semiconductor integrated circuit A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply ... | 05/17/2011 |
| 7915926 | Semiconductor chip and semiconductor device including the same A semiconductor chip includes a plurality of pads, input circuits or output circuits that are electrically connected to the pads, a main control unit that outputs a read access signal, the read access signal controlling reading of signals from an external circuit or... | 03/29/2011 |
| 7906990 | Semiconductor integrated circuit device The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor ... | 03/15/2011 |
| 7902879 | Field programmable gate array utilizing dedicated memory stacks in a vertical layer format A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable ... | 03/08/2011 |
| 7855579 | Semiconductor integrated circuit and design method thereof In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed,... | 12/21/2010 |
| 7843226 | Semiconductor integrated circuit device and test terminal arrangement method A semiconductor integrated circuit device includes a column of first logic circuit cells arranged along a first side of a chip and a column of second logic circuit cells arranged along a second side orthogonal to the first side. At a corner part where the first side... | 11/30/2010 |
| 7808280 | Semiconductor device A semiconductor device includes multiple functional blocks, each having a predetermined function, and wiring regions on a substrate where a signal line is provided. The semiconductor device also includes multiple standard cells disposed in the wiring regions along t... | 10/05/2010 |
| 7800409 | Logic block, a multi-track standard cell library, a method of designing a logic block and an asic employing the logic block A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block in... | 09/21/2010 |
| 7768314 | Integrated circuit with multidimensional switch topology An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potentia... | 08/03/2010 |
| 7759979 | Gate driving circuit A gate driving circuit includes a first output buffer unit region, a level shifter region and a low voltage circuit region. The first output buffer unit region is formed on a plane and is utilized for setting a first output buffer unit. The level shifter region is f... | 07/20/2010 |
| 7755396 | Power network using standard cell, power gating cell, and semiconductor device using the power network A low power semiconductor memory device using a power gating is disclosed. The semiconductor memory device includes a standard cell and a power gating cell. The standard cell is provided with a virtual supply voltage and a first supply voltage. The power gating cell... | 07/13/2010 |
| 7750681 | Semiconductor integrated circuit A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply ... | 07/06/2010 |
| 7741878 | Semiconductor integrated circuit with leakage current suppressed In a semiconductor integrated circuit, a cell arrangement area is provided on a semiconductor substrate to allow a plurality of basis cells to be arranged. A basic power supply line is provided in an upper layer than the cell arrangement area to supply a power. A sw... | 06/22/2010 |
| 7696788 | Semiconductor integrated circuit A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of g... | 04/13/2010 |
| 7649386 | Field programmable gate array utilizing dedicated memory stacks in a vertical layer format A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable ... | 01/19/2010 |
| 7589566 | Semiconductor device provided with antenna ratio countermeasure circuit A CMOS LSI includes an inverter including first and second MOS transistors, a relatively long metal interconnection connected to an input node of the inverter, first and second diodes releasing charges born by the metal interconnection during a plasma process to fir... | 09/15/2009 |
| 7548095 | Isolation scheme for static and dynamic FPGA partial programming An isolation scheme to permit partial programming of FPGA integrated circuits controlled by Flash memory cells includes a p-type semiconductor region. First and second spaced apart deep n-wells are disposed in the p-type semiconductor region. First and second p-well... | 06/16/2009 |
| 7518409 | Input stage of semiconductor device with multiple pads of common function, and multi-chip package having the same An input stage of a semiconductor device includes at least two pads, input buffers, a current source, and a logic operation circuit. The at least two pads, to which the input buffers respectively correspond, perform a common function. The current source provides a c... | 04/14/2009 |
| 7511536 | Cells of a customizable logic array device having independently accessible circuit elements Various embodiments of the invention provide for cell structures having independently accessible circuit elements as a part of a customizable logic array device. In one embodiment, a cell forming a portion of a customizable logic array device includes a base layer, ... | 03/31/2009 |
| 7456659 | Semiconductor integrated circuit A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of g... | 11/25/2008 |
| 7439767 | Semiconductor integrated circuit and construction using densely integrated cells A semiconductor integrated circuit having a first cell row including a plurality of cells disposed in a row direction, each cell having a prescribed cell width in the row direction and at least one input pin provided at a prescribed location in the row direction; an... | 10/21/2008 |
| 7432732 | Integrated circuit device including interface circuit and electronic apparatus An integrated circuit device, includes: an input pad region including a differential signal input region receiving a pair of differential signals, a first power supply input region and a second power supply input region; and an interface circuit including a receivin... | 10/07/2008 |
| 7423453 | Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric Efficient layout schemes to implement switching networks of an interconnection fabric in an integrated circuit to connect two sets of conductors through rows of switches with prescribed number of tracks over the switching area are described. The layout schemes can b... | 09/09/2008 |
| 7420392 | Programmable gate array and embedded circuitry initialization and processing Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting... | 09/02/2008 |
