Bizarre Patents
Reward Candy Dispenser for Personal Computers
A personal computer peripheral, battery powered reward candy dispenser which immediately presents students with a single candy for each problem completed correctly.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8138796 | Serial configuration interface A serial configuration interface (SCI) used to configure a device is disclosed. A device that support SCI includes a first connector configured to receive a first signal and a second connector configured to receive a second signal. In a configuration mode, the first... | 03/20/2012 |
| 8089301 | Inverter and logic device comprising the same The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transist... | 01/03/2012 |
| 8072243 | Semiconductor device with transistors having substantial the same characteristic variations A semiconductor device is provided. The semiconductor device includes a first circuit provided between a power source voltage line and a ground line, including at least two first MOS transistors coupled in parallel and a second circuit, which is provided between the... | 12/06/2011 |
| 8004315 | Process for making and designing an IC with pattern controlled layout regions The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient... | 08/23/2011 |
| 7969199 | Pattern controlled IC layout The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient... | 06/28/2011 |
| 7965107 | Base cell for engineering change order (ECO) implementation A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pa... | 06/21/2011 |
| 7944243 | Semiconductor integrated circuit A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply ... | 05/17/2011 |
| 7915926 | Semiconductor chip and semiconductor device including the same A semiconductor chip includes a plurality of pads, input circuits or output circuits that are electrically connected to the pads, a main control unit that outputs a read access signal, the read access signal controlling reading of signals from an external circuit or... | 03/29/2011 |
| 7906990 | Semiconductor integrated circuit device The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor ... | 03/15/2011 |
| 7902879 | Field programmable gate array utilizing dedicated memory stacks in a vertical layer format A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable ... | 03/08/2011 |
| 7855579 | Semiconductor integrated circuit and design method thereof In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed,... | 12/21/2010 |
| 7843226 | Semiconductor integrated circuit device and test terminal arrangement method A semiconductor integrated circuit device includes a column of first logic circuit cells arranged along a first side of a chip and a column of second logic circuit cells arranged along a second side orthogonal to the first side. At a corner part where the first side... | 11/30/2010 |
| 7808280 | Semiconductor device A semiconductor device includes multiple functional blocks, each having a predetermined function, and wiring regions on a substrate where a signal line is provided. The semiconductor device also includes multiple standard cells disposed in the wiring regions along t... | 10/05/2010 |
| 7800409 | Logic block, a multi-track standard cell library, a method of designing a logic block and an asic employing the logic block A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block in... | 09/21/2010 |
| 7768314 | Integrated circuit with multidimensional switch topology An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potentia... | 08/03/2010 |
| 7759979 | Gate driving circuit A gate driving circuit includes a first output buffer unit region, a level shifter region and a low voltage circuit region. The first output buffer unit region is formed on a plane and is utilized for setting a first output buffer unit. The level shifter region is f... | 07/20/2010 |
| 7755396 | Power network using standard cell, power gating cell, and semiconductor device using the power network A low power semiconductor memory device using a power gating is disclosed. The semiconductor memory device includes a standard cell and a power gating cell. The standard cell is provided with a virtual supply voltage and a first supply voltage. The power gating cell... | 07/13/2010 |
| 7750681 | Semiconductor integrated circuit A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply ... | 07/06/2010 |
| 7741878 | Semiconductor integrated circuit with leakage current suppressed In a semiconductor integrated circuit, a cell arrangement area is provided on a semiconductor substrate to allow a plurality of basis cells to be arranged. A basic power supply line is provided in an upper layer than the cell arrangement area to supply a power. A sw... | 06/22/2010 |
| 7696788 | Semiconductor integrated circuit A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of g... | 04/13/2010 |
| 7649386 | Field programmable gate array utilizing dedicated memory stacks in a vertical layer format A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable ... | 01/19/2010 |
| 7589566 | Semiconductor device provided with antenna ratio countermeasure circuit A CMOS LSI includes an inverter including first and second MOS transistors, a relatively long metal interconnection connected to an input node of the inverter, first and second diodes releasing charges born by the metal interconnection during a plasma process to fir... | 09/15/2009 |
| 7548095 | Isolation scheme for static and dynamic FPGA partial programming An isolation scheme to permit partial programming of FPGA integrated circuits controlled by Flash memory cells includes a p-type semiconductor region. First and second spaced apart deep n-wells are disposed in the p-type semiconductor region. First and second p-well... | 06/16/2009 |
| 7518409 | Input stage of semiconductor device with multiple pads of common function, and multi-chip package having the same An input stage of a semiconductor device includes at least two pads, input buffers, a current source, and a logic operation circuit. The at least two pads, to which the input buffers respectively correspond, perform a common function. The current source provides a c... | 04/14/2009 |
| 7511536 | Cells of a customizable logic array device having independently accessible circuit elements Various embodiments of the invention provide for cell structures having independently accessible circuit elements as a part of a customizable logic array device. In one embodiment, a cell forming a portion of a customizable logic array device includes a base layer, ... | 03/31/2009 |
| 7456659 | Semiconductor integrated circuit A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of g... | 11/25/2008 |
| 7439767 | Semiconductor integrated circuit and construction using densely integrated cells A semiconductor integrated circuit having a first cell row including a plurality of cells disposed in a row direction, each cell having a prescribed cell width in the row direction and at least one input pin provided at a prescribed location in the row direction; an... | 10/21/2008 |
| 7432732 | Integrated circuit device including interface circuit and electronic apparatus An integrated circuit device, includes: an input pad region including a differential signal input region receiving a pair of differential signals, a first power supply input region and a second power supply input region; and an interface circuit including a receivin... | 10/07/2008 |
| 7423453 | Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric Efficient layout schemes to implement switching networks of an interconnection fabric in an integrated circuit to connect two sets of conductors through rows of switches with prescribed number of tracks over the switching area are described. The layout schemes can b... | 09/09/2008 |
| 7420392 | Programmable gate array and embedded circuitry initialization and processing Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting... | 09/02/2008 |
| 7417457 | Scalable non-blocking switching network for programmable logic A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect substantially a first plurality of conductors, through a first set of switches, to a second plurality sets of conductors. The conductors i... | 08/26/2008 |
| 7414437 | Nanomechanical computer An electromechanical switching device employs a first nanoscale pillar shuttling charge between opposed charged electrodes. Motion of the first pillar is coupled to a second set of pillars providing controlled charge transfer between a second isolated set of electro... | 08/19/2008 |
| 7409659 | System and method for suppressing crosstalk glitch in digital circuits A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed.... | 08/05/2008 |
| 7388401 | Input/output circuit device An input/output circuit device includes a first transistor which is formed at a substrate, a first gate of which receives an input signal, one of a first source and drain of which is connected to a first power supply terminal, and the other of the first source and d... | 06/17/2008 |
| 7382157 | Interconnect driver circuits for dynamic logic Interconnect driver circuits that can be used in the interconnect structures of dynamic integrated circuits (ICs) such as dynamic programmable logic devices (PLDs). An exemplary IC includes two or more logic circuits, and two or more self-resetting interconnect driv... | 06/03/2008 |
| 7378874 | Creating high-drive logic devices from standard gates with minimal use of custom masks Logic cells in an application-specific integrated circuit (ASIC) emulating standard gate sizing by duplicating elements within a single standard gate where logical high-drive gates are synthesized and converted to parallel elements as a post-process. The drive chara... | 05/27/2008 |
| 7378871 | Programmable device with structure for storing configuration information In a programmable cell included in a first region, configuration information is stored in a volatile memory, while in a programmable cell included in a second region, configuration information is stored in a non-volatile memory. Configuration information for a sub-p... | 05/27/2008 |
| 7375553 | Clock tree network in a field programmable gate array A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elemen... | 05/20/2008 |
| 7375548 | SCL type FPGA with multi-threshold transistors and method for forming same A new scheme of Schottky FPGA (SFPGA) IC solution is proposed. The chip is organized by embedded analog, memory, and logic units with on chip apparatus and software means to partitioning, altering selected portions of hardware. The process means is based on the comb... | 05/20/2008 |
| 7372298 | Chip with adjustable pinout function and method thereof A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a second port. The selecting circuit, which is coupled to the logic circu... | 05/13/2008 |
