Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 8174284 | Repairable IO in an integrated circuit Methods and structures for implementing repairable input/output (IO) circuitry in an integrated circuit (IC) are disclosed. One embodiment of the present invention includes repairable IO circuitry along a right, left, or inner column of an IC. Another embodiment inc... | 05/08/2012 |
| 8013627 | Semiconductor device and method of fabricating the same Provided is a semiconductor device and a method of fabricating the same. The semiconductor device may include at least one logic circuit and at least one spare circuit. The at least one spare circuit may be that is a substitute for the at least one logic circuit and... | 09/06/2011 |
| 7906984 | Relocatable field programmable gate array bitstreams for fault tolerance A Field Programmable Gate Array (FPGA) circuit capable of operating through at least one fault. The FPGA circuit includes a configuration memory and an embedded microprocessor. The embedded microprocessor having access to the configuration memory, static modules, at... | 03/15/2011 |
| 7902855 | Repairable IO in an integrated circuit Methods and structures for implementing repairable input/output (IO) circuitry in an integrated circuit (IC) arc disclosed. One embodiment of the present invention includes repairable IO circuitry along a right, left, or inner column of an IC. Another embodiment inc... | 03/08/2011 |
| 7852107 | Single event upset mitigation In one embodiment of the invention, a method is provided for protecting against single event upsets of a circuit in programmable logic. Configuration memory cells of the programmable logic are configured to implement first and second copies of the circuit. In respon... | 12/14/2010 |
| 7772872 | Multi-row block supporting row level redundancy in a PLD In a Programmable Logic Device (PLD), a multi-row block that has internal logic connections between rows has redundant internal connections between rows to replace the internal logic connections when a fault occurs. The redundant internal logic connections extend th... | 08/10/2010 |
| 7646209 | Semiconductor integrated circuit and method of production of same A semiconductor integrated circuit, able to repair a fault and normally operate as an overall circuit even when a fault occurs in a portion of the circuit, and able to reduce a change of signal delay along with the repair of the fault, including N (larger than 2) nu... | 01/12/2010 |
| 7619438 | Methods of enabling the use of a defective programmable device Methods of enabling the use of defective programmable devices. The method comprises performing functional testing for each programmable device of a plurality of programmable devices; identifying each programmable device of the plurality of programmable devices havin... | 11/17/2009 |
| 7612577 | Speedpath repair in an integrated circuit A circuit comprises a first plurality of transistors of a first channel length disposed along a speedpath, the first plurality of transistors providing a first timing performance. The circuit also comprises a second plurality of transistors of a second channel lengt... | 11/03/2009 |
| 7609083 | Semiconductor integrated circuit device and storage apparatus having the same A semiconductor integrated circuit device includes: a first large scale integrated circuit including a plurality of first logical blocks; a programmable second large scale integrated circuit connected the first large scale integrated circuit and including a second l... | 10/27/2009 |
| 7598765 | Redundant configuration memory systems and methods Systems and methods are disclosed directed to techniques with respect to defective configuration memory cells. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of configuration memory cells; and... | 10/06/2009 |
| 7589552 | Integrated circuit with redundancy Integrated circuits such as programmable logic devices are provided that have circuit blocks such as memory blocks. The integrated circuits may be tested to determine whether the circuit blocks contain defects. If defective circuitry is identified, switching circuit... | 09/15/2009 |
| 7550992 | Logic cell with two isolated redundant outputs, and corresponding integrated circuit The disclosure relates to a logic cell for an integrated circuit, including two redundant outputs, a first output equipped with an output transistor of type P and a second output equipped with an output transistor of type N. Such a cell includes isolation element co... | 06/23/2009 |
| 7508231 | Programmable logic device having redundancy with logic element granularity A PLD having logic element row granularity redundancy is disclosed. The PLD includes a plurality of LABs arranged in an array and a plurality of horizontal and vertical inter-LAB lines interconnecting the LABs of the array. Each of the LABs further includes a predet... | 03/24/2009 |
| 7443191 | Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the rou... | 10/28/2008 |
| 7429870 | Resilient integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 09/30/2008 |
| 7427871 | Fault tolerant integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 09/23/2008 |
| 7423448 | Radiation hardened logic circuit A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitr... | 09/09/2008 |
| 7411412 | Semiconductor integrated circuit A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modu... | 08/12/2008 |
| 7411411 | Methods and systems for hardening a clocked latch against single event effects Methods and systems for hardening a clocked latch against single event effects are disclosed. A system includes a first three-input OR gate, a first NAND gate, a second three-input OR gate, and a second NAND gate. The first three-input OR gate receives as inputs a c... | 08/12/2008 |
| 7408380 | Method and apparatus for a redundant transceiver architecture A method and apparatus to provide various mechanisms to improve yield of an integrated circuit (IC) employing serial input/output (I/O) communication devices. A single error correction model provides one spare transceiver per group of primary transceivers, whereby r... | 08/05/2008 |
| 7405990 | Method and apparatus for in-system redundant array repair on integrated circuits Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit wit... | 07/29/2008 |
| 7397709 | Method and apparatus for in-system redundant array repair on integrated circuits Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit wit... | 07/08/2008 |
| 7373567 | System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented... | 05/13/2008 |
| 7362628 | Semiconductor memory and redundancy repair method In a semiconductor memory in which redundancy repair is carried out on a block basis, when a defective block of memory cells is replaced by a first redundant block, the adjacent normal block of memory cells closest to the defect, or a part of that normal block, is a... | 04/22/2008 |
| 7362697 | Self-healing chip-to-chip interface A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path i... | 04/22/2008 |
| 7345506 | Redundancy method and software to provide improved interconnect efficiency for programmable logic devices A method and computer readable medium for implementing redundancy on a programmable logic device with improved interconnect efficiency. The method and medium includes: determining if a first wire segment of a first wire channel requires a programmed connection to a ... | 03/18/2008 |
| 7336102 | Error correcting logic system The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redu... | 02/26/2008 |
| 7336115 | Redundancy in signal distribution trees A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in t... | 02/26/2008 |
| 7328379 | Look-up table for use with redundant memory A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuit... | 02/05/2008 |
| 7321518 | Apparatus and methods for providing redundancy in integrated circuits An integrated circuit (IC) includes a redundancy feature. The redundancy feature is provided by a redundancy circuitry within the IC. The redundancy circuitry is configured to provide the redundancy by using a decoder circuitry. The decoder circuitry receives and de... | 01/22/2008 |
| 7310278 | Method and apparatus for in-system redundant array repair on integrated circuits Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit wit... | 12/18/2007 |
| 7301362 | Duplicated double checking production rule set for fault-tolerant electronics Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The... | 11/27/2007 |
| 7298168 | Method and apparatus for error mitigation of programmable logic device configuration memory A method and apparatus to reduce the probability of programmable logic device (PLD) failure due to single event upset (SEU) of configuration memory. A first portion of configuration memory cells are initially programmed with configuration data, leaving a second port... | 11/20/2007 |
| 7292060 | Logic circuit and method thereof An example embodiment of the present invention relates to a method of executing a logic operation while remaining safe from side channel attacks. Another example embodiment of the present invention relates to a logic circuit and device for executing a logic operatio... | 11/06/2007 |
| 7289382 | Rewritable fuse memory An apparatus includes a first fuse, a second fuse and a circuit. The circuit uses the first fuse to indicate a stored value for a fuse memory location, and in response to the fuse memory location being rewritten, the circuit uses the second fuse to indicate the stor... | 10/30/2007 |
| 7286020 | Techniques for monitoring and replacing circuits to maintain high performance Techniques are provided for monitoring the performance of circuits and replacing low performing circuits with higher performing circuits. A frequency detector compares the frequency of a first periodic signal to the frequency of a second periodic signal. The differe... | 10/23/2007 |
| 7287177 | Digital reliability monitor having autonomic repair and notification capability An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when... | 10/23/2007 |
| 7277346 | Method and system for hard failure repairs in the field A semiconductor system and method for repairing failures of a packaged integrated circuit system are provided. The method includes detecting a failure associated with a packaged integrated circuit system after the packaged integrated circuit system is packaged, and ... | 10/02/2007 |
| 7276931 | System and method for creating replacements for obsolete computer chips A system and method for replacing a malfunctioning logic device with a substitute logic device. The system provides a replacement assembly that contains a complex programmable logic device, a programming port and a pin configuration. The pin configuration selected m... | 10/02/2007 |
