Did You Know...
...that Charles Goodyear performed some of his experiments on rubber while in debtor's prison? He was there so often he referred to it as his "hotel". Chronically in debt because of poor business sense and ill health, Goodyear depended on the generosity of friends and family. Even after he unlocked the secret to vulcanizing rubber, he was unable to improve his financial situation. When he died, his estate was $200,000 in debt.
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| Number | Title | Issue Date |
| 8004306 | Semiconductor device A semiconductor device according to an embodiment of the present invention includes: an oscillating circuit including a plurality of logic circuits connected in series; and an error detecting circuit receiving output signals of at least two of the plurality of logic... | 08/23/2011 |
| 7994811 | Test device and semiconductor integrated circuit device Test devices and integrated circuits with improved productivity are provided. In accordance with example embodiments, a test device may include a first test region with a first test element and a second test region with a second test element defined on a semiconduct... | 08/09/2011 |
| 7969177 | System and method for thermal limit control This disclosure relates to a system and method for pulse generation. A system in accordance with the present disclosure may include a power dissipating element configured to receive power from a power source. At least one of the power source and the power dissipatin... | 06/28/2011 |
| 7948259 | Dielectric film and layer testing A system for testing and a method for making a semiconductor device is disclosed. A preferred embodiment includes a conductor overlying a dielectric layer. The conductor is coupled to a first test pad via a first conducting line and to a second test pad via a second... | 05/24/2011 |
| 7928755 | Methods and apparatus that selectively use or bypass a remote pin electronics block to test at least one device under test In one embodiment, apparatus for testing at least one device under test (DUT) includes a tester input/output (I/O) node, a DUT I/O node, a remote pin electronics block, a bypass circuit, and a control system. The remote pin electronics block provides a test function... | 04/19/2011 |
| 7906982 | Interface apparatus and methods of testing integrated circuits using the same An apparatus and method are provided for testing a semiconductor device (DUT). Generally, the apparatus includes an interface board with conductive elements adapted to electrically couple with the DUT and connected to a number of test circuits. Each test circuit res... | 03/15/2011 |
| 7902853 | Semiconductor device, semiconductor device testing method, and probe card A test signal to be supplied to a driver section when the driver section is subjected to an operation test is generated by a test circuit. In the test circuit, the test signal can be generated by a burn-in control circuit in accordance with a clock signal TESTCK sup... | 03/08/2011 |
| 7898280 | Electrical characterization of semiconductor materials A system and method for characterizing electronic properties of a semiconductor sample includes illuminating the surface of the semiconductor sample with a pulse of light, measuring a photoconductance decay in the semiconductor sample after the cessation of the firs... | 03/01/2011 |
| 7888961 | Apparatus and method for electrical detection and localization of shorts in metal interconnect lines A test structure for localizing shorts in an integrated circuit and method of testing is described. A first comb structure is formed from a first busbar and a first plurality of fingers extending from the first busbar. A second comb structure formed from a second bu... | 02/15/2011 |
| 7884634 | High density interconnect system having rapid fabrication cycle An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mou... | 02/08/2011 |
| 7884633 | Wide area soft defect localization Various apparatus and methods of testing a semiconductor chip for soft defects are disclosed. In one aspect, a method of testing a semiconductor chip that has a surface and plural circuit structures positioned beneath the surface is provided. An external stimulus is... | 02/08/2011 |
| 7880494 | Accurate capacitance measurement for ultra large scale integrated circuits Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. T... | 02/01/2011 |
| 7876121 | Link analysis compliance and calibration verification for automated printed wiring board test systems A transmission line on a printed wiring board is tested and printed wiring board manufacturing variability is assessed. A response of the transmission line to a signal test pattern is measured. A network including a plurality of components connected by the transmiss... | 01/25/2011 |
| 7872489 | Radiation induced fault analysis A method of locating a defect of a failed semiconductor device which includes applying a test pattern to the failed semiconductor device and providing failed semiconductor device test responses as a pass signature, applying radiation to each of multiple locations of... | 01/18/2011 |
| 7872488 | Tester for testing semiconductor device A tester for testing a semiconductor device is disclosed. In accordance with the tester of the present invention, the tester is configured to have different drive signal path and input/output signal path wherein the drive signal path has a fly-by structure, i.e. a d... | 01/18/2011 |
| 7868640 | Array-based early threshold voltage recovery characterization measurement A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early st... | 01/11/2011 |
| 7868639 | Methods and apparatus for integrated circuit loopback testing Methods and apparatus are provided for performing loopback testing of integrated circuits (“ICs”). In an embodiment of the invention, an IC can be tested on an undiced wafer by coupling a wireless transmitter of the IC to a wireless receiver of the IC. Core circ... | 01/11/2011 |
| 7868642 | Socket for connecting ball-grid-array integrated circuit device to test circuit A simple structure socket 10 for connecting a ball grid array integrated circuit device to a test circuit has a base 14, contacts 26 arranged corresponding to the ball grid array, a nest assembly 16 of two comb structures 70 and a ... | 01/11/2011 |
| 7868641 | Semiconductor device A semiconductor device with technology for externally deciding if the stress test was performed or not. A semiconductor device includes a stress test circuit and a stress test decision circuit. The stress test circuit outputs control signals for executing the stress... | 01/11/2011 |
| 7863920 | Electrostatic discharge test system and electrostatic discharge test method A method of conducting an electrostatic discharge test on an integrated circuit is described. The method comprises configuring a test board assembly to emulate characteristics of a system in which the integrated circuit is to be used, coupling the integrated circuit... | 01/04/2011 |
| 7863921 | Circuit board and method for automatic testing A circuit board (CB) and method for automatic testing of an electronic device under test (DUT). The circuit board (CB) has a first terminal (T1) for coupling to automatic test equipment (ATE) including a first signal generator (SG1), a second terminal ... | 01/04/2011 |
| 7863922 | Evaluation method of insulating film and measurement circuit thereof Provided is a method of evaluating dielectric breakdown by applying a current to an insulating film, in which measurement for a forward direction current and measurement for a backward direction current are performed in a short period of time. For this purpose two M... | 01/04/2011 |
| 7863924 | Pusher assemblies for use in microfeature device testing, systems with pusher assemblies, and methods for using such pusher assemblies Pusher assemblies for use in microelectronic device testing systems and methods for using such pusher assemblies are disclosed herein. One particular embodiment of such a pusher assembly comprises a plate having a first side and a second side opposite the first side... | 01/04/2011 |
| 7863923 | Adaptive test time reduction for wafer-level testing In a method for testing a plurality of consecutively indexed sites, a default test sequence is applied to the consecutively indexed sites until a first defective site is identified. If a first defective site is identified, then a more stringent test sequence is appl... | 01/04/2011 |
| 7859288 | Test apparatus and test method for testing a device based on quiescent current Provided is A test apparatus that tests a device under test, including a power supply section that supplies power to a power supply terminal of the device under test; a power supply control section that controls the power supply section to output the power at a plur... | 12/28/2010 |
| 7859275 | Parallel scan distributors and collectors and process of testing integrated circuits An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional cir... | 12/28/2010 |
| 7859289 | Method for measuring interface traps in thin gate oxide MOSFETS A method for measuring interface traps in a MOSFET, includes measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined f... | 12/28/2010 |
| 7859287 | Device power supply extension circuit, test system including the same and method of testing semiconductor devices A test system includes a controller, a power supply circuit and a device power supply (DPS) extension circuit. The controller controls a test operation for a plurality of devices under test (DUTs). The power supply circuit generates a common power voltage in respons... | 12/28/2010 |
| 7859286 | Electronic device test system When the number of DUTs carried on a loader buffer and scheduled to be held by contact arms at the next test is less than N, a DUT at a contact arm corresponding to a missing position at the loader buffer among the N number of DUTs being held for execution of a curr... | 12/28/2010 |
| 7855571 | Testing circuit board for preventing tested chip positions from being wrongly positioned A testing circuit board used in a testing system with a tester and a handler is disclosed. The testing circuit board is used for transmitting a plurality of testing signals provided by the tester to test at least two devices under test located on the handler. The te... | 12/21/2010 |
| 7855572 | Semiconductor integrated circuit device operating frequency determining apparatus, determining method and computer-readable information recording medium A variation in manufacturing total costs is obtained by using an excessive loss amount caused by unnecessarily discarding elemental semiconductor integrated circuits occurring as a result of a negative result being obtained in an elemental test but a positive result... | 12/21/2010 |
| 7852101 | Semiconductor device testing apparatus and power supply unit for semiconductor device testing apparatus The semiconductor device testing apparatus has a testing LSI; a power supply unit; and an intermediate substrate. The testing LSI has a dielectric material layer facing a tested semiconductor device; an electrode disposed in a position corresponding to a position of... | 12/14/2010 |
| 7852103 | Implementing at-speed Wafer Final Test (WFT) with complete chip coverage A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) ... | 12/14/2010 |
| 7852102 | Method and apparatus for inspecting semiconductor device The magnitude of an amplitude waveform of an electromagnetic wave generated when irradiating a pulse laser beam to a structure A including diffusion regions provided in the structure of a semiconductor device to be inspected is compared with the magnitude of an ampl... | 12/14/2010 |
| 7847576 | Comparator with latching function A comparison amplification unit compares a level of a signal in a positive line with that of a signal in a negative line and latches a comparison result. An input terminal of a first inverter is connected to the positive line and an output terminal thereof is connec... | 12/07/2010 |
| 7847574 | Semiconductor device When a stop condition is satisfied, a stop condition determination circuit (10) issues a stop instruction to an operation stop control circuit (11) to stop the operation of a functional circuit (14). A storage device (12) stores therein d... | 12/07/2010 |
| 7847573 | Test apparatus and performance board Provided is a test apparatus for testing a device under test, including: a plurality of signal supply sections that output test signals at different timing from each other; and a connection section that connects lines of wiring transmitting the test signals respecti... | 12/07/2010 |
| 7847575 | Method and apparatus for nano probing a semiconductor chip Various methods and apparatus for electrically probe testing a semiconductor chip with circuit perturbation are disclosed. In one aspect, a method of testing is provided that includes contacting a first nano probe to a conductor structure on a first side of a semico... | 12/07/2010 |
| 7843207 | Methods and apparatus to test electronic devices Methods and apparatus to test electronic devices are disclosed. An example method includes setting a first controlled switch to prevent a current detect signal from tripping an overcurrent protection event controlling an operation of the device; setting a second con... | 11/30/2010 |
| 7839159 | ZQ calibration circuit and a semiconductor device including a ZQ calibration circuit A ZQ calibration command is internally generated from an external command different from a ZQ calibration command so as to automatically perform an additional ZQ calibration operation. A command interval between an inputted command and a next command is effectively ... | 11/23/2010 |
