Bizarre Patents
Mouthguard made at least partially from an edible candy
A mouthguard includes a U-shaped upper bite plate which removably fits over upper teeth of a person, with the entire upper bite plate being made from a soft, deformable and edible gummi candy.
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| Number | Title | Issue Date |
| 7821282 | Inverter that calculates an average value of direct current DC An inverter has an inverter circuit and a current detector. In the inverter circuit, upper-arm switching elements and lower-arm switching elements, which are connected to DC power supply, provide DC with pulse-width modulation (PWM) so as to output AC to a load. The... | 10/26/2010 |
| 7746092 | Intelligent multi-meter with automatic function selection A measuring device with the function of automatically determining the type of device under test (DUT) and selecting measuring function. The measuring device having a controller for sequentially providing a plurality of checking phases; a protection circuit connectin... | 06/29/2010 |
| 7439730 | Apparatus and method for detecting photon emissions from transistors A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the... | 10/21/2008 |
| 7403029 | Massively parallel interface for electronic circuit Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules... | 07/22/2008 |
| 7372289 | Semiconductor integrated circuit device and power supply voltage monitor system employing it A semiconductor integrated circuit device, i.e. a reset IC(1), includes: a detection circuit (4) for detecting whether an input voltage (Vin) has risen or dropped by comparing the input voltage (Vin) with a reference voltage; a delay circuit (8)... | 05/13/2008 |
| 7368678 | Method for sorting integrated circuit devices A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their auto... | 05/06/2008 |
| 7348791 | High voltage, high frequency, high reliability, high density, high temperature automated test equipment (ATE) switch design An electronic switching apparatus for use in automated test equipment. The electronic switching apparatus includes a transconducting device having source and drain regions where at least one of the source and drain regions is configured to be coupled to a voltage so... | 03/25/2008 |
| RE40188 | System and method for providing an integrated circuit with a unique identification An integrated circuit identification device (ICID) to be incorporated into an integrated circuit (IC) includes an array of electronic cells in which the magnitude of an output signal of each cell is a function of randomly occurring parametric variations which vary f... | 03/25/2008 |
| 7340359 | Augmenting semiconductor's devices quality and reliability A method for augmenting quality or reliability of semiconductor units, including providing few populations of semiconductor units that are subject to quality or reliability testing. The populations include few quality or reliability fail candidate populations and ot... | 03/04/2008 |
| 7337088 | Intelligent measurement modular semiconductor parametric test system An intelligent measurement modular semiconductor parametric test system comprises an engine control module. The engine control module is operable to communicate with a user via a user interface, and is further operable to communicate with and to control the state of... | 02/26/2008 |
| 7327158 | Array testing method using electric bias stress for TFT array A method of detecting thin film transistor (TFT) defects in a TFT-liquid crystal display (LCD) panel, includes, in part, applying a stress bias to the TFTs disposed on the panel; and detecting a change in electrical characteristics of the TFTs. The change in the ele... | 02/05/2008 |
| 7323862 | Apparatus and method for detecting photon emissions from transistors A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the... | 01/29/2008 |
| 7323899 | System and method for resumed probing of a wafer According to one embodiment of the invention, a method for resuming the probing of a wafer includes identifying a data set associated with a wafer. The data set identifies at least one unprobed die supported on the surface of the wafer. The method also includes dete... | 01/29/2008 |
| 7323897 | Mock wafer, system calibrated using mock wafer, and method for calibrating automated test equipment In one embodiment, a mock wafer for calibrating automated test equipment includes a printed circuit board having a number of interconnect areas, with each interconnect area having a pair of mock die pads that are coupled via a connecting trace. In another embodiment... | 01/29/2008 |
| 7317325 | Line short localization in LCD pixel arrays A method and apparatus for identifying a location of a short between two or more signal lines on a substrate having a plurality of thin film transistors and a plurality of pixels associated with the thin film transistors. The method includes locating the two or more... | 01/08/2008 |
| 7282943 | Inspection device for inspecting TFT Provided is an inspection device which inspects a thin film transistor (TFT) for supplying a current to a light emitting element. The inspection device includes: a first current supply circuit which supplies a drain current between a drain and a source of the TFT; a... | 10/16/2007 |
| 7282377 | Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip In the manufacturing process of a semiconductor integrated circuit device, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical amount corresponding to variations in the process of the plurality of... | 10/16/2007 |
| 7279920 | Expeditious and low cost testing of RFID ICs System and method for integrated circuit manufacturing. A preferred embodiment comprises transmitting a first set of data to integrated circuits (ICs) while they are in an on-wafer state and having each IC store the first set of data into memory, transmitting a seco... | 10/09/2007 |
| 7265567 | First die indicator for integrated circuit wafer An integrated circuit (IC) wafer includes a plurality of die and a first die indicator (FDI) formed on the wafer in a metal layer. The plurality of die include a first potentially good die and the FDI, which is detectable by a machine vision recognition system, prov... | 09/04/2007 |
| 7265568 | Semi-conductor component test process and a system for testing semi-conductor components A semi-conductor component test process, and a system for testing semi-conductor components, with which several different semi-conductor-component tests can be conducted in succession. A computer installation, in particular a test apparatus is provided, with which t... | 09/04/2007 |
| 7257504 | Production of radio frequency ID tags A radio frequency ID tag, very small in size and with an onboard antenna, is manufactured, tested and applied cost-efficiently. The transmit frequency for the tag is set during manufacture approximately, within a selected range, in a gross tuning step. A second tuni... | 08/14/2007 |
| 7238543 | Methods for marking a bare semiconductor die including applying a tape having energy-markable properties A method used for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cros... | 07/03/2007 |
| 7230442 | Semi-conductor component testing process and system for testing semi-conductor components The invention involves a semi-conductor component testing process, and a system for testing semi-conductor components, in which a central computer device, in particular a central test apparatus is provided, with which test result data obtained from at least two sepa... | 06/12/2007 |
| 7231552 | Method and apparatus for independent control of devices under test connected in parallel A JTAG-compatible device includes a unique identifier stored in dedicated non-volatile memory, a test access port (TAP) controller, a TAP instruction register, a dedicated data register, and a comparison block. The TAP instruction register enables and/or disables TA... | 06/12/2007 |
| 7219418 | Method to prevent damage to probe card Probe cards are configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. Protective fuses are provided in electrical communication with conductive traces and probe elements (e.g., probe need... | 05/22/2007 |
| 7162386 | Dynamically adaptable semiconductor parametric testing An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time based on statistical thresholds or other selected criteria. Each map may include a series of locations on a ... | 01/09/2007 |
| 7149885 | Automatic concealment of expansion cards in computer system In a computer system selectively operable in multiple operating systems, supported-card identification information identifying types of expansion cards supported by respective ones of the operating systems is previously stored. An unsupported expansion card is deter... | 12/12/2006 |
| 7148716 | System and method for the probing of a wafer According to one embodiment of the invention, a method for resuming the probing of a wafer includes identifying a data set associated with a wafer. The data set identifies at least one unprobed die supported on the surface of the wafer. The method also includes dete... | 12/12/2006 |
| 7138818 | Massively parallel interface for electronic circuit Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules... | 11/21/2006 |
| 7139672 | Dynamically adaptable semiconductor parametric testing An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time based on statistical thresholds or other selected criteria. Each map may include a series of locations on a ... | 11/21/2006 |
| 7137014 | Apparatus, method and program product for automatically distributing power to modules within a server In a chassis based server a programmed processor determines the fabric type that allows the maximum numbers of processor modules and switches to be powered on. The processor then allows power to be applied to processor modules and switches whose fabric type is the s... | 11/14/2006 |
| 7134599 | Circuit board inspection apparatus A circuit board inspection apparatus aims to inspect a circuit board panel which contains a plurality of sub-panels. The panel is bonded with a panel barcode and each sub-panel is bonded with a different sub-panel barcode. The circuit board inspection apparatus incl... | 11/14/2006 |
| 7126226 | Semiconductor device and semiconductor chip for use therein A semiconductor device has a first semiconductor chip and a second semiconductor chip superposed on and bonded to the surface of the first semiconductor chip. In the region on the first semiconductor chip where the second semiconductor chip is bonded thereto, connec... | 10/24/2006 |
| 7106609 | Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces betwee... | 09/12/2006 |
| 7094618 | Methods for marking a packaged semiconductor die including applying tape and subsequently marking the tape The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The pr... | 08/22/2006 |
| 7053645 | System and method for detecting defects in a thin-film-transistor array A system and method for detecting a defect in a transistor array includes applying a test signal to the array, monitoring pixel voltages along a gate line of the array, and detecting a defect associated with the gate line based on a variation in the pixel voltages a... | 05/30/2006 |
| 7031791 | Method and system for a reject management protocol within a back-end integrated circuit manufacturing process A method and system for a reject management protocol within a back-end IC manufacturing process. In one method embodiment, the present invention implements a tracking process for a die-strip. The present invention also maintains an electronic die-strip map database,... | 04/18/2006 |
| 7012443 | System used to test plurality of DUTs in parallel and method thereof Provided is a system and method of testing a plurality of devices under test (DUTs) in parallel. The method includes preparing at least two DUTs having input/output signal pins connected in common to one input/output signal channel and having chip selection signal p... | 03/14/2006 |
| 7010451 | Dynamic creation and modification of wafer test maps during wafer testing Methods, systems, and apparatuses provide dynamic creation and modification of wafer test maps. Test plans are defined for a testing session of a wafer lot. The test plan is associated with a number of seed map patterns. During a wafer lot testing session, test resu... | 03/07/2006 |
| 6996484 | Sequential unique marking The present invention comprises a method of sequential unique marking comprising providing a multi-die handling device with a plurality of semiconductor devices therein, reading an ID code on the multi-die handling device, retrieving a tray map file corresponding to... | 02/07/2006 |
