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| Number | Title | Issue Date |
| 7804290 | Event-driven time-interval measurement An apparatus including a circuit configured to measure timing between features in a first signal only referring to timing information contained in the signal itself. ... | 09/28/2010 |
| 7791330 | On-chip jitter measurement circuit An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, the circuit including a latch for latching and comparing the arrival time of the signal of interest to the reference clock, a clock ... | 09/07/2010 |
| 7439724 | On-chip jitter measurement circuit An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communica... | 10/21/2008 |
| 7375506 | Device for comparing an input signal with a set value and correspondinng electronic circuit A comparison device includes a one-threshold comparator receiving an input signal and a set value and generating a resultant signal. The comparison device further includes a sampler for sampling the resultant signal and a controller for blocking the sampler, after a... | 05/20/2008 |
| 7368954 | Phase comparison circuit and CDR circuit Providing a CDR circuit having a stable clock extracting function and a data regenerating function with a high-speed data input process by reducing the operation speed of the phase comparator circuit. With a phase comparator circuit capable of operating with a clock... | 05/06/2008 |
| 7362107 | Systems and methods for automatically eliminating imbalance between signals A calibrating system for automatically eliminating or reducing imbalance between a first signal and a second signal is disclosed. The calibrating system includes: a programmable delay module, receiving to the first and the second signals; a phase detecting module, c... | 04/22/2008 |
| 7337083 | Process for identification of the direction of rotation of two periodic electrical signals at the same frequency A process and apparatus for identification of the direction of rotation of two periodic electrical signals present on two electrical conductors, particularly of a three-phase power system. In this process, the signals are sampled from two conductors by two wires of ... | 02/26/2008 |
| 7336084 | Delay lock circuit having self-calibrating loop A delay lock circuit includes a measuring path, a forward path, and a feedback path. The measuring path samples a pulse with a reference signal in a measurement to obtain a measured delay. The forward path delays the reference signal based on the measured delay to g... | 02/26/2008 |
| 7317309 | Wideband signal analyzing apparatus, wideband period jitter analyzing apparatus, and wideband skew analyzing apparatus A wideband signal analyzing apparatus for analyzing an input signal includes frequency-shifting means for generating a plurality of intermediate frequency signals by shifting a frequency of the input signal as much as respectively different frequency-shifting amount... | 01/08/2008 |
| 7313178 | Transceiver for receiving and transmitting data over a network and method for testing the same The present invention provides a transceiver for receiving and transmitting data over a network, and a method for testing the same. In particular, the present invention provides a physical layer transceiver having a built-in-self-test (BIST) device that allows for, ... | 12/25/2007 |
| 7288973 | Method and apparatus for fail-safe resynchronization with minimum latency A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and v... | 10/30/2007 |
| 7263153 | Clock offset compensator A device communicates with a host and includes a transmitter, a receiver and a clock generator that generates a signal having a local clock frequency. A clock recovery circuit communicates with the receiver and recovers a host clock frequency from data received from... | 08/28/2007 |
| 7253674 | Output clock phase-alignment circuit A clock generator has a reset circuit and (at least) two dividers, where each divider divides a reference clock signal by a divisor value to generate an output clock signal. The reset circuit generates reset signals for the dividers, where the reset signals are dela... | 08/07/2007 |
| 7227395 | High-performance memory interface circuit architecture A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digita... | 06/05/2007 |
| 7203229 | Apparatus for and method of measuring jitter A signal under measurement is band-limited, and frequency components around a fundamental frequency of the signal under measurement are extracted. Waveform data (approximated zero-crossing data) close to zero-crossing timings of the band-limited signal are sampled, ... | 04/10/2007 |
| 7202656 | Methods and structure for improved high-speed TDF testing using on-chip PLL Methods and structure for improved high-speed TDF testing using an on-chip PLL and associated logic to generate high speed launch and capture pulses. A reference clock may be applied to a PLL circuit within the integrated circuit under test to generate a higher freq... | 04/10/2007 |
| 7154437 | Method and system for processing positioning signals based on predetermined message data segment A method and system for determining a geolocation of an object includes collecting a positioning signal including a predetermined message data segment. A time of arrival of the predetermined message data segment may be determined in the positioning signal. Informati... | 12/26/2006 |
| 7119523 | Semiconductor chip A semiconductor chip able to reduce wasteful power loss due to a margin of power supply voltage considering variation of characteristics. A voltage setting signal for setting the power supply voltage to be supplied to a target circuit is generated in a voltage contr... | 10/10/2006 |
| 7110932 | Method and circuit arrangement for regulating the operating voltage of a digital circuit A method and circuit arrangement for determining performance of a digital circuit to a critical degree by the transit time of signals of the longest signal path, also called the critical path. Since the signal transit time is influenced by the operating voltage, by ... | 09/19/2006 |
| 7075310 | Device and method for testing for a wiring fault condition A device for testing for a wiring fault condition is disclosed. The device includes an electrical connector, a first signal generator, a second signal generator, and a user interface. The electrical connector includes first and second contacts that are configured to... | 07/11/2006 |
| 7071676 | Circuit configuration and method for measuring at least one operating parameter for an integrated circuit A circuit configuration for measuring at least one operating parameter for an integrated circuit includes an analysis circuit connected to at least one external connection on the integrated circuit. The analysis circuit detects a plurality of voltage level changes o... | 07/04/2006 |
| 7062663 | Voltage regulation in an integrated circuit The invention relates to power regulation of integrated circuits such as microprocessors. It suggests measuring instantaneous power consumption inside of the integrated circuit (13), by sensing state changes of the transistors of the units (14, 16, 18 20, ... | 06/13/2006 |
| 7057553 | Method and system for processing positioning signals in a stand-alone mode A method for processing positioning signals in a ranging receiver in a stand-alone mode is provided. The method includes collecting pseudorange samples from positioning signals received at the ranging receiver from a plurality of satellites. The pseudorange samples ... | 06/06/2006 |
| 7027545 | Data sampler for digital frequency/phase determination The present invention, generally speaking, provides a digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a know... | 04/11/2006 |
| 7019532 | Device and method for error diagnosis at digital outputs of a control module A device for identifying a wire break between an electrical connection of a digital output and a load includes an evaluation module connected to the electrical connection and a voltage limiter module also connected to the electrical connection for co-determining a v... | 03/28/2006 |
| 7012982 | Method and system for de-jittering of transmitted MPEG-2 and MPEG-4 video The present invention relates to an improved method of de-jittering MPEG-2 and MPEG-4 data that is transmitted over a network. First, a network system jitter associated with periodic reference data packets is estimated. Then, the estimated system jitter is used to a... | 03/14/2006 |
| 7012418 | Measuring system with ratiometric frequency output A measuring device, with a digital interface for the transmission of digital signals to an evaluation unit, is disclosed, whereby the interface includes a clock input, to which a system clock signal is fed, a signal input, to which a measured signal is applied, an a... | 03/14/2006 |
| 7002358 | Method and apparatus for measuring jitter A method of measuring jitter includes generating a jitter pulse having a width corresponding to an amount of jitter. The jitter pulse is provided to a plurality (M) of latches serially coupled to successively trim the pulse as it propagates through the serially coup... | 02/21/2006 |
| 6999548 | Communication channel detector and channel detection method A communications channel detector which determines the availability of a desired type of communications channel in a communication system having at least one communications channel, the communications channels including data streams comprising a number of data symbo... | 02/14/2006 |
| 6992958 | Phase-locked loop circuit for reproducing a channel clock In PLL circuits for reproducing a channel clock in synchronism with data read from a disk-shaped recording medium driven for rotation, the frequency dividing ratio of frequency dividers provided in desired signal paths is made changeable according to the reproduced ... | 01/31/2006 |
| 6977950 | Power distribution network for optoelectronic circuits Method and arrangement are disclosed for a power distribution network for distributing power to VCSELS on an optoelectronic chip that maintains a constant bias voltage to the VCSELs. More particularly, the power distribution network includes an H-tree network for di... | 12/20/2005 |
| 6969984 | Direct phase and frequency demodulation The present invention, generally speaking, provides a time shift angle demodulator that is of simple construction and has an extended linear range. Range extension is achieved by using the input signals directly, not simply post-processing the S-PFD outputs. In acco... | 11/29/2005 |
| 6949958 | Phase comparator capable of tolerating a non-50% duty-cycle clocks A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and v... | 09/27/2005 |
| 6937070 | Amplitude-detecting method and circuit Two all pass filters (11, 12) with 90° phase-shifted different center frequencies are employed to pass an alternating signal S with jitters in the period to generate signals S1 and S2, 90° phase-shifted from each other. A pulse generator (2... | 08/30/2005 |
| 6759838 | Phase-locked loop with dual-mode phase/frequency detection A phase-locked loop with dual-mode phase/frequency detection is provided. The phase-locked loop circuit includes a dual-mode phase/frequency detector, a loop filter, a voltage-controlled oscillator, and a frequency converter. In addition, the dual-mode phase/frequen... | 07/06/2004 |
| 6735543 | Method and apparatus for testing, characterizing and tuning a chip interface An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing... | 05/11/2004 |
| 6639413 | System and method for calibration of data in an electric power monitoring system The error compensating system and method is used in electric power monitoring systems, e.g. protective relays, and includes a test unit for applying a test signal to the front end of a data acquisition section of the power monitoring system and a phase re... | 10/28/2003 |
| 6538834 | Servo controller and servo control method A servo controller for correcting a read position of a head when reading data recorded on a recording medium. In accordance with the amplitude ratio of data signals read from each segment of a servo section defined on a recording medium, the servo control... | 03/25/2003 |
| 6535049 | Multipurpose test chip input/output circuit A system for testing an integrated circuit. The system includes a plurality of simultaneous switching output (SSO) cells with each of the plurality of simultaneous SSO cells including an output driver providing an output signal to a respective signal pin ... | 03/18/2003 |
| 6528982 | Jitter detector, phase difference detector and jitter detecting method A jitter detector obtains a phase difference between input signals as a digital value to make jitter between the signals easily detectable. The jitter detector includes comparison pulse generator, periodic signal generator, counter and arithmetic unit. Th... | 03/04/2003 |
