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| Number | Title | Issue Date |
| 7812593 | Method for improving stability and lock time for synchronous circuits Delay-locked loops, signal locking methods and devices incorporating delay-locked loops are described. A delay-locked loop includes a forward loop path, a feedback loop path, and a phase detector. A test clock signal is temporarily switched to traverse the forward l... | 10/12/2010 |
| 7705581 | Electronic device and method for on chip jitter measurement The present invention relates to an integrated electronic device for digital signal processing, which includes a reference clock input for receiving a reference clock, a phase locked loop (PLL), a phase interpolator (PI) coupled to the phase locked loop (PLL) for sh... | 04/27/2010 |
| 7459899 | Inductively-coupled RF power source A system and method are disclosed for implementing a power source including a power amplifier that generates a radio-frequency power signal with an adjustable operating frequency. The power amplifier also generates a reference phase signal that is derived from the r... | 12/02/2008 |
| 7439723 | Communicating with an implanted wireless sensor The present invention determines the resonant frequency of a sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low dut... | 10/21/2008 |
| 7411463 | Method, system, apparatus, and program for measuring the damping factor of an Nth order phase locked loop (PLL) A method for measuring the damping factor of an Nth-order phase-locked loop, wherein N>1, and a system, apparatus, and program that operate in accordance with the method. The method includes applying a modulation source at an input to the phase-locked loo... | 08/12/2008 |
| 7400130 | Integrated circuit device An integrated circuit device comprises internally on-chip an oscillator with a signal output. The device has a reference clock input, a first counter with a count input, a control input and a counter output, a second counter with a count input, a control input and a... | 07/15/2008 |
| 7362184 | Frequency divider monitor of phase lock loop A circuit and method for monitoring a frequency divider. The circuit including a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedbac... | 04/22/2008 |
| 7356102 | Gain compensation over temperature and frequency variations in wireless transceivers Systems and methods are provided for controlling gain compensation over temperature and frequency variations. A variable amplifier may be used to receive a control signal and an input signal. The variable amplifier may be operable to apply a gain to the input signal... | 04/08/2008 |
| 7355487 | Method for reducing phase lock time and jittering and phase lock loop using the same A method for reducing phase lock time and jittering and a phase lock loop (PLL) using the same adapted for PLL including a charge pump (CP) which includes a pull-up and a pull-down networks used for controlling output voltage of the CP. The output voltage is used fo... | 04/08/2008 |
| 7355380 | Methods and apparatus for testing delay locked loops and clock skew According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the 360° signal and on the 180° signal. The delay in... | 04/08/2008 |
| 7352190 | Calibration apparatus, calibration method, and testing apparatus A jitter measuring circuit includes a jitter signal generating section that generates a jitter signal, and an integrating section that charges and discharges a capacitor with a predetermined electric current according to the jitter signal to integrate the jitter sig... | 04/01/2008 |
| 7352165 | Delay-locked loop and a method of testing a delay-locked loop A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test ... | 04/01/2008 |
| 7349283 | Integrated semiconductor memory An integrated semiconductor memory includes a test mode control circuit and at least one voltage generator for generating an operating voltage that is fed into memory banks via interconnects. Comparator circuits are arranged at locations along the respective interco... | 03/25/2008 |
| 7342426 | PLL with controlled VCO bias In some embodiments, a PLL with an output to provide a PLL output clock at a target frequency is provided. The PLL comprises a VCO to generate a clock to be used to generate the PLL output clock. Also provided is circuitry to maintain the VCO's bias level at a suffi... | 03/11/2008 |
| 7343139 | Device for converting frequencies, method of calibrating said device and system for transmitting/receiving electromagnetic signals comprising such a device The invention relates to a device for converting frequencies comprising a local oscillator of fixed frequency and a first mixer with two inputs and an output, a first input receiving the signal to be converted and a second input receiving the signal arising from the... | 03/11/2008 |
| 7336084 | Delay lock circuit having self-calibrating loop A delay lock circuit includes a measuring path, a forward path, and a feedback path. The measuring path samples a pulse with a reference signal in a measurement to obtain a measured delay. The forward path delays the reference signal based on the measured delay to g... | 02/26/2008 |
| 7323914 | Charge pump circuit Adverse effects of switching noise produced by a charge pump circuit on a displayed image are prevented. In a synchronizing separation circuit 18, a synchronizing signal is separated from a video signal. The separated synchronizing signal is subjected to ½ f... | 01/29/2008 |
| 7295643 | Method and a device for phase and frequency comparison The phase and frequency comparator for controlling, as a function of the frequency (Fref) and the phase of a reference signal (Sref), the frequency (Fvco) and the phase of the output signal of a controlled-frequency oscillator compri... | 11/13/2007 |
| 7292044 | Integrating time measurement circuit for a channel of a test card In a first embodiment of the invention there is provided an electronic chip for use with an automatic testing equipment device testing a device under test. The device under test has a plurality of pins and the electronic chip is placed in a channel of a test card th... | 11/06/2007 |
| 7285948 | Method and apparatus providing single cable bi-directional triggering between instruments System and apparatus enabling the use of a single cable to communicate triggering information between each of a plurality of signal acquisition devices and, illustratively, an external trigger control unit. A combined tripper signal is produced only when each trippe... | 10/23/2007 |
| 7274200 | Semiconductor circuit, method of monitoring semiconductor-circuit performance, method of testing semiconductor circuit, equipment for testing semiconductor circuit, and program for testing semiconductor circuit A semiconductor circuit is disclosed, including a DLL circuit for supplying a desired signal-delay amount. The DLL circuit includes detecting means for detecting variations of a signal-delay amount, and delay-amount control means for generating a delay-amount contro... | 09/25/2007 |
| 7265637 | Startup/yank circuit for self-biased phase-locked loops An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, ... | 09/04/2007 |
| 7263628 | Method and apparatus for receiver circuit tuning A Mobile Subscriber Directory Assistance (MSDA) system including originating carrier center initiating a directory assistance call, a directory assistance center providing a directory assistance service, and a search environment. The search environment includes an a... | 08/28/2007 |
| 7259604 | Initialization scheme for a reduced-frequency, fifty percent duty cycle corrector A reduced-frequency, 50% duty cycle corrector (DCC) circuit may be used in an electronic device (e.g., a memory chip) to generate output clocks with 50% duty cycle irrespective of the duty cycle of the clock input to the DCC circuit. A DCC initialization scheme sele... | 08/21/2007 |
| 7256629 | Phase-locked loops A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control signal and a square root module configured to receive state information, the state information corresponding to tuning information, the square root module fu... | 08/14/2007 |
| 7246025 | Method and apparatus for synchronizing signals in a testing system The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal.... | 07/17/2007 |
| 7245540 | Controller for delay locked loop circuits A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal. The DLL constantly responds to variations in operating condition of the memory device to keep the external... | 07/17/2007 |
| 7245117 | Communicating with implanted wireless sensor The present invention determines the resonant frequency of a sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low dut... | 07/17/2007 |
| 7242730 | Mirror suppression circuit and receiver using such circuit A mirror suppression circuit includes a first quadrature signal path coupled between quadrature signal input and output terminals and an error correction circuit for correction of amplitude and phase errors in a carrier modulated quadrature signal. To obtain a suppr... | 07/10/2007 |
| 7221138 | Method and apparatus for measuring charge pump output current A method for measuring output current of a charge pump, the method including providing a charge pump including a plurality of n charge pump stages, wherein an output of stage n−1(Von−1) is output to stage n, an output voltage of stage n being referred... | 05/22/2007 |
| 7221727 | All-digital phase modulator/demodulator using multi-phase clocks and digital PLL Multi-phase clocks are used to encode and decode signals that are phase-modulated. The input signal is phase-compared with a feedback clock. Phase differences increment or decrement an up/down counter. The count value from the up/down counter is applied to a phase r... | 05/22/2007 |
| 7202656 | Methods and structure for improved high-speed TDF testing using on-chip PLL Methods and structure for improved high-speed TDF testing using an on-chip PLL and associated logic to generate high speed launch and capture pulses. A reference clock may be applied to a PLL circuit within the integrated circuit under test to generate a higher freq... | 04/10/2007 |
| 7184936 | Timing variation measurement system and method The present invention is a system and method that facilitates measurement of timing variations (e.g., timing delays) in a semiconductor chip. The timing variations are measured and presented as digital values without extensive off chip measurement and analysis equip... | 02/27/2007 |
| 7177381 | Noise-resistive, burst-mode receiving apparatus and a method for recovering a clock signal and data therefrom A noise-resistive, burst-mode receiving apparatus including a voltage control signal generator for multiplying a frequency of a system clock signal and generating a voltage control signal having a level that corresponds to the multiplied frequency; a reset signal ge... | 02/13/2007 |
| 7173461 | Self-biased phased-locked loop In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input and a second control input, wherein the first control input and the second control input act to control output frequency ... | 02/06/2007 |
| 7171183 | Linearized fractional-N synthesizer having a current offset charge pump A linear fractional-N synthesizer includes phase and frequency detection module, a charge pump circuit, a loop filter, a voltage controlled oscillator, and a fractional-N divider. The phase and frequency detection module is operably coupled to produce a charge up si... | 01/30/2007 |
| 7167093 | Method of steering capacitor fields for use in capacitive sensing security systems The present invention provides a capacitive sensing apparatus having utility in object detection security applications whereby the object detection field generated by the apparatus is made steerable. The apparatus includes a power source having a ground connection i... | 01/23/2007 |
| 7158443 | Delay-lock loop and method adapting itself to operate over a wide frequency range A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A... | 01/02/2007 |
| 7151814 | Hogge phase detector with adjustable phase output A system and method are provided for adjusting the phase output of a Hogge phase detector. The method comprises: using a Hogge phase detector, generating a reference signal; using the Hogge phase detector, generating a phase and reference signals; accepting an adjus... | 12/19/2006 |
| 7142025 | Phase difference detector, particularly for a PLL circuit A phase difference detector adapted to generating a signal indicative of a phase difference between a first signal and a second signal, comprising: a first bistable element clocked by the first signal and having a first output signal, and a second bistable element c... | 11/28/2006 |
