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| Number | Title | Issue Date |
| 7208753 | Enhancement mode single electron transistor A transistor having a bottom dielectric layer, a first layer, a second layer, a top dielectric layer, and a gate electrode. The first layer and the second layer form a composite quantum well between the bottom dielectric layer and the top dielectric layer. The first... | 04/24/2007 |
| 6459120 | Semiconductor device and manufacturing method of the same A regular tetrahedral groove is formed in a wafer, and a memory unit is formed, which includes a channel layer as a first semiconductor layer to serve as a channel, a three-layer structure floating layer as a second semiconductor layer to serve as a float... | 10/01/2002 |
| 6133603 | Memory device and memory array It is made possible to conduct writing and erasing information at high speed and with a low gate voltage, attain high integration with reduced power dissipation, and retain information accurately. It is also made possible to change the conductivity of a c... | 10/17/2000 |
| 6080995 | Quantum device A quantum device functioning as a memory device is provided for allowing high-speed writing and erasing of data with a low gate voltage. A source electrode and a drain electrode are formed on a substrate. A gate electrode is formed between the source and ... | 06/27/2000 |
| 6023079 | Compound semiconductor memory with floating gate A compound semiconductor memory has a second semiconductor layer (undoped AlGaAs hetero-barrier layer), a third semiconductor layer (n type InGaAs layer), a fourth semiconductor layer (undoped AlGaAs layer) and a gate electrode of WSi selectively deposite... | 02/08/2000 |
| 5432356 | Semiconductor heterojunction floating layer memory device and method for storing information in the same A semiconductor memory device comprises a non-doped thick barrier layer formed on the semiconductor substrate, an impurity doped floating conducting layer formed on the thick barrier layer, a thin barrier layer formed on the floating conducting layer and ... | 07/11/1995 |
| 5055890 | Nonvolatile semiconductor memory having three dimension charge confinement A layered semiconductor device with a nonvolatile three dimensional memory comprises a storage channel which stores charge carriers. Charge carriers flow laterally through the storage channel from a source to a drain. Isolation material, either a Schottky... | 10/08/1991 |
| 4945393 | Floating gate memory circuit and apparatus A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially ... | 07/31/1990 |
| 4905063 | Floating gate memories A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially ... | 02/27/1990 |
| 4903092 | Real space electron transfer device using hot electron injection Real space hot electron transfer devices using hot electron transfer between two conducting channels are described.... | 02/20/1990 |
| 4698652 | FET with Fermi level pinning between channel and heavily doped semiconductor gate Herein disclosed is a semiconductor device in which control means for carriers migrating in a first semiconductor includes an interface state layer lying on the first semiconductor and a second conductor layer lying on the interface state layer. The inter... | 10/06/1987 |
