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A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
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| Number | Title | Issue Date |
| 7405452 | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region m... | 07/29/2008 |
| 7279368 | Method of manufacturing a vertical junction field effect transistor having an epitaxial gate A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is for... | 10/09/2007 |
| 7276754 | Annular gate and technique for fabricating an annular gate A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surfac... | 10/02/2007 |
| 6696706 | Structure and method for a junction field effect transistor with reduced gate capacitance An apparatus and method for a semiconductor device with reduced gate capacitance. Specifically, an n-channel or p-channel junction field effect transistor (JFET) is described comprising an appropriately doped substrate forming a drain region, an epitaxial... | 02/24/2004 |
| 6693314 | Junction field-effect transistor with more highly doped connecting region A junction field-effect transistor containing a semiconductor region with an inner region is described. In addition, a first and a second connecting region, respectively, are disposed within the semiconductor region. The first connecting region has the sa... | 02/17/2004 |
| 6693322 | Semiconductor construction with buried island region and contact region A semiconductor configuration for current control has an n-type first semiconductor region with a first surface, a p-type covered island region, within the first semiconductor region, with a second surface, an n-type contact region arranged on the second ... | 02/17/2004 |
| 6690040 | Vertical replacement-gate junction field-effect transistor A vertical JFET architecture. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of differ... | 02/10/2004 |
| 6653666 | J-FET semiconductor configuration J-FET having a first semiconductor region (2, 3), which comprises a first contact (7) with a highly doped contact layer (8) serving as a source disposed between two second contacts (9) serving as a gate on its first surface (4). The three contacts (7, 9) ... | 11/25/2003 |
| 6576929 | Silicon carbide semiconductor device and manufacturing method A channel layer 4 is formed on an n- -type epitaxial layer 2 and first gate areas 3, and field enhanced area(s) 5 and second gate areas 6 are formed on the first gate areas 3. Furthermore, n+ -type source areas 7 and a third gate are... | 06/10/2003 |
| 6551865 | Silicon carbide semiconductor device and method of fabricating the same Openings are formed in a laminate of a polycrystalline silicon film and an LTO film on a channel layer. While the laminate is used as a mask, impurities are implanted into a place in the channel layer which is assigned to a source region. Also, impurities... | 04/22/2003 |
| 6459108 | Semiconductor configuration and current limiting device The semiconductor configuration is formed with a lateral channel region and an adjoining vertical channel region in an n-conductive first semiconductor region. When a predetermined saturation current is exceeded, the lateral channel region is pinched off ... | 10/01/2002 |
| 6429457 | Field-effect transistor A field-effect transistor is made with electrodes (2, 4, 5) and isolators (3) in vertically provided layers, such that at least the electrodes (4, 5) and the isolators (3) form a step (6) oriented vertically relative to the first electrode (2) or the subs... | 08/06/2002 |
| 6313482 | Silicon carbide power devices having trench-based silicon carbide charge coupling regions therein Silicon carbide power devices having trench-based charge coupling regions include a silicon carbide substrate having a silicon carbide drift region of first conductivity type (e.g., N-type) and a trench therein at a first face thereof. A uniformly doped s... | 11/06/2001 |
| 6291242 | Methods for generating polynucleotides having desired characteristics by iterative selection and recombination A method for DNA reassembly after random fragmentation, and its application to mutagenesis of nucleic acid sequences by in vitro or in vivo recombination is described. In particular, a method for the production of nucleic acid fragments or polynucleotides... | 09/18/2001 |
| 6285046 | Controllable semiconductor structure with improved switching properties The invention concerns a controllable semiconductor structure comprising a base region (101, 201, 301, 401), a source region (106, 212, 312, 412) and a drain region (107, 213, 313, 413) a conductive duct being provided in the base region between the sourc... | 09/04/2001 |
| 6281521 | Silicon carbide horizontal channel buffered gate semiconductor devices Silicon carbide channel semiconductor devices are provided which eliminate the insulator of the gate by utilizing a semiconductor gate layer and buried base regions to create a "pinched off" gate region when no bias is applied to the gate. In particular e... | 08/28/2001 |
| 6274904 | Edge structure and drift region for a semiconductor component and production method The invention relates to an edge structure and a drift region for a semiconductor component. A semiconductor body of the one conductivity type has an edge area with a plurality of regions of the other conductivity type embedded in at least two mutually di... | 08/14/2001 |
| 6255710 | 3-D smart power IC An integrated smart power circuit including a power semiconductor device fabricated on a conducting substrate with a source positioned adjacent the upper surface of the substrate, a control terminal between the upper and lower surfaces, and a drain positi... | 07/03/2001 |
| 6232625 | Semiconductor configuration and use thereof A semiconductor configuration, in particular based on silicon carbide, is specified which rapidly limits a short-circuit current to an acceptable current value. For this purpose, when a predetermined saturation current is exceeded, a lateral channel regio... | 05/15/2001 |
| 6188555 | Device for limiting alternating electric currents, in particular in the event of a short circuit A device for limiting an alternating electric current includes a least one passive semiconductor configuration and a protection circuit. The semiconductor configuration is configured such that when a forward voltage is applied thereto, a forward current f... | 02/13/2001 |
| 6127695 | Lateral field effect transistor of SiC, a method for production thereof and a use of such a transistor A lateral field effect transistor of SiC for high switching frequencies comprises a source region layer (5) and a drain region layer (6) laterally spaced and highly doped n-type, an n-type channel layer (4) extending laterally and interconnecting the sour... | 10/03/2000 |
| 6117735 | Silicon carbide vertical FET and method for manufacturing the same In a method for forming a silicon carbide vertical FET, a first mask and a second mask that overlaps the first mask are used so that a first conductivity type impurity region is defined by one end of a certain portion of the first mask, and that portion o... | 09/12/2000 |
| 6097046 | Vertical field effect transistor and diode A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).... | 08/01/2000 |
| 6037618 | Intergrated field effect transistor device for high power and voltage amplification of RF signals An integrated transistor device operates with a linear triode vacuum tube like characteristic with a very low output impedance and a large interaction between the gate and drain potentials. The drain current of a first transistor is connected directly to ... | 03/14/2000 |
| 6034385 | Current-limiting semiconductor configuration A semiconductor configuration includes a first semiconductor region which has a predetermined conductivity type and a first surface. There is a contact region disposed on the first surface of the first semiconductor region. There is a second semiconductor... | 03/07/2000 |
| 5963807 | Silicon carbide field effect transistor with increased avalanche withstand capability A vertical SiC trench MOSFET power switching FET includes a gate electrode in the trench. The MOSFET adds a buried region of a first conductivity type, more heavily doped than a base layer of the first conductivity type, to the base layer except adjacent ... | 10/05/1999 |
| 5945699 | Reduce width, differentially doped vertical JFET device A load device for an MOS transistor, such as that of a memory cell, includes a differentially doped vertical JFET structure that contains two separate and distinct opposite conductivity type regions. The interior region has the same conductivity as the we... | 08/31/1999 |
| 5910665 | Low capacitance power VFET method and device A method and structure for a vertical FET transistor device (VFET) is described for a lower junction capacitance VFET to decrease the switching power loss and achieve increased current capacity and/or deceased thermal dissipation. In a preferred embodimen... | 06/08/1999 |
| 5895931 | Semiconductor device A barrier layer (AlAs) is formed on a source layer (n-GaAs), and a drain layer (n-GaAs) and a gate layer (p-GaAs) adjacent to the drain layer are formed on the barrier layer. If the drain layer is biased to a plus voltage with the source layer, then a tun... | 04/20/1999 |
| 5895939 | Silicon carbide field effect transistor with increased avalanche withstand capability A vertical SiC trench MOSFET power switching FET includes a gate electrode in the trench. The MOSFET adds a buried region of a first conductivity type, more heavily doped than a base layer of the first conductivity type, to the base layer except adjacent ... | 04/20/1999 |
| 5793055 | Hybrid electronic devices, particularly Josephson transistors A step junction is provided for superconductor/semiconductor heterostructure hybrid devices like tunneling transistors, in a body of p-InAs with a vertical side connecting the low plateau and high plateau on which superconductors, preferably of niobium, a... | 08/11/1998 |
| 5747842 | Epitaxial overgrowth method and devices A vertical field effect transistor (100) and fabrication method with buried gates; (104) having spaced apart gate fingers and connecting structure and overgrown with source and channel epilayer followed by a doping connection of the gate fingers and conne... | 05/05/1998 |
| 5747831 | SIC field-effect transistor array with ring type trenches and method of producing them SiC field-effect transistors with source, gate and drain contacts and in which the source contacts are located on the surface of the semiconductor wafer, the drain contacts on the underside of the wafer and the gate contacts in trench-like structures. The... | 05/05/1998 |
| 5736753 | Semiconductor device for improved power conversion having a hexagonal-system single-crystal silicon carbide To provide a field-effect transistor having a large power conversion capacity and its fabrication method by decreasing the leakage current between the source and the drain of a semiconductor device made of hexagonal-system silicon carbide when the gate vo... | 04/07/1998 |
| 5714777 | Si/SiGe vertical junction field effect transistor A junction field effect transistor and method for making is described incorporating horizontal semiconductor layers within an opening to form a channel and a semiconductor layer through which the opening was made which forms a gate electrode surrounding t... | 02/03/1998 |
| 5705406 | Method for producing a semiconductor device having semiconductor layers of SiC by the use of an ion-implantation technique A method for producing a semiconductor device having semiconductor layers of SiC with at least three doped layers on top of each other, comprises the steps of growing a first semiconductor layer of SiC; implanting an impurity dopant into the first layer t... | 01/06/1998 |
| 5661318 | Junction type field-effect transistor A junction type field-effect transistor in accordance with the invention includes a multi-layer structure which includes a first undoped semiconductor layer, a first first-conductive type semiconductor layer and a second undoped semiconductor layer. These... | 08/26/1997 |
| 5648664 | BIFET vacuum tube replacement structure A BIFET vacuum tube replacement structure includes a plurality of devices that replicate the characteristics of a vacuum tube. The vacuum tube replacement structure has the same pin-out as the vacuum tube being replaced and so can be exchanged directly fo... | 07/15/1997 |
| 5610085 | Method of making a vertical FET using epitaxial overgrowth A vertical field effect transistor (1700) and fabrication method with buried gates (1704) having spaced apart gate fingers and connecting structure and overgrown with source and channel epilayer followed by a doping connection of the gate fingers and conn... | 03/11/1997 |
| 5599724 | FET having part of active region formed in semiconductor layer in through hole formed in gate electrode and method for manufacturing the same An N-type source (or drain) region is formed in the surface area of a P-type silicon substrate. A first insulation film is formed on the silicon substrate and a gate electrode is formed on the first insulation film. A second insulation film is formed on t... | 02/04/1997 |
