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| Number | Title | Issue Date |
| 7315056 | Semiconductor memory array of floating gate memory cells with program/erase and select gates A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an el... | 01/01/2008 |
| 7253429 | Electrically programmable memory element A programmable resistance memory element including a memory material which is raised above a semiconductor substrate by a dielectric layer. ... | 08/07/2007 |
| 7166886 | DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A storage... | 01/23/2007 |
| 6703298 | Self-aligned process for fabricating memory cells with two isolated floating gates A self-aligned process for fabricating a non-volatile memory cell having two isolated floating gates. The process includes forming a gate dielectric layer over a semiconductor substrate. A floating gate layer is then formed over the gate dielectric layer.... | 03/09/2004 |
| 6690058 | Self-aligned multi-bit flash memory cell and its contactless flash memory array A self-aligned multi-bit flash memory cell of the present invention comprises two floating-gate structures with a spacing dielectric layer being formed therebetween; a planarized control-gate layer over an intergate-dielectric layer being formed over the ... | 02/10/2004 |
| 6674122 | Semiconductor integrated circuit A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete t... | 01/06/2004 |
| 6674133 | Twin bit cell flash memory device The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1-x Gex | 01/06/2004 |
| 6670669 | Multiple-bit non-volatile memory utilizing non-conductive charge trapping gate The invention is to provide a novel non-volatile memory capable of recording multi-bit data. The invention is a non-volatile memory which has: first and second source-drain regions SD1, SD2 at the surface of a semiconductor substrate; and a non-conductive... | 12/30/2003 |
| 6657253 | Memory of multilevel quantum dot structure and method for fabricating the same Memory of a multilevel quantum dot structure and a method for fabricating the same, is disclosed, the method including the steps of (1) forming a first insulating layer on a substrate, (2) repeating formation of a conductive layer and a second insulating ... | 12/02/2003 |
| 6649972 | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping A programmable, read only memory device includes two diffusion areas in a substrate and a channel formed therebetween, an oxide-nitride-oxide (ONO) layer comprising a first oxide layer overlaid by a nitride layer overlaid by a second oxide layer, the nitr... | 11/18/2003 |
| 6649470 | Dual floating gate programmable read only memory cell structure and method for its fabrication and operation A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while source and drain regions are connected ... | 11/18/2003 |
| 6627927 | Dual-bit flash memory cells for forming high-density memory arrays The dual-bit flash memory cells of the present invention include three regions: the gate region, the first-side region, and the second-side region. The gate region is formed between the first-side region and the second-side region and is defined by a mask... | 09/30/2003 |
| 6614069 | Nonvolatile semiconductor memory cell and method for fabricating the memory cell A nonvolatile semiconductor memory cell includes a transistor component formed on a substrate and a storage node that determines the switching state of the transistor component. The storage node is arranged near a control gate electrode. The storage node ... | 09/02/2003 |
| 6597036 | Multi-value single electron memory using double-quantum dot and driving method thereof A multi-value single electron memory using a multi-quantum dot, in which the floating gates (FG) of a EEPROM or a flash memory are formed to act as two quantum dots, and the two quantum dots are applied to multi-value memories, and a driving method of the... | 07/22/2003 |
| 6573140 | Process for making a dual bit memory device with isolated polysilicon floating gates The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 b... | 06/03/2003 |
| 6566707 | Transistor, semiconductor memory and method of fabricating the same A plurality of source/drain regions are formed on a surface of a silicon substrate at a prescribed space. Floating gate electrodes are formed on sides of a channel region closer to the source/drain regions respectively through a first insulator film. Proj... | 05/20/2003 |
| 6545314 | Memory using insulator traps A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density o... | 04/08/2003 |
| 6538292 | Twin bit cell flash memory device A semiconductor wafer comprises a semiconductor substrate of a first conductive type, a source and a drain of a second conductive type positioned in predetermined areas of the semiconductor substrate, and a channel positioned on the surface of the semicon... | 03/25/2003 |
| 6531735 | Semiconductor integrated circuit A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete t... | 03/11/2003 |
| 6504756 | Dual floating gate programmable read only memory cell structure and method for its fabrication and operation A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while active doped regions (source and drain ... | 01/07/2003 |
| 6504755 | Semiconductor memory device A semiconductor memory device is constituted by forming two types of insulation films on the channel of an MOS transistor on which a vertical type another MOS transistor using the control gate of the MOS transistor as a substrate is stacked. Thus, a non-v... | 01/07/2003 |
| 6504206 | Split gate flash cell for multiple storage In this invention polysilicon sidewalls on a semiconductor substrate are used as split gate flash memory cells. The sidewalls are formed around a core of silicon nitride and left standing once the silicon nitride is removed. Bit lines are implanted into t... | 01/07/2003 |
| 6501680 | Nonvolatile memory, cell array thereof, and method for sensing data therefrom Nonvolatile memory, cell array thereof, and method for sensing a data therefrom, the method including the steps of: selecting a flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and ... | 12/31/2002 |
| 6492228 | Dual floating gate programmable read only memory cell structure and method for its fabrication and operation A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while source and drain regions are connected ... | 12/10/2002 |
| 6479858 | Method and apparatus for a semiconductor device with adjustable threshold voltage The present invention provides a semiconductor device with a channel length of approximately 0.05 microns. A semiconductor device according to the present invention, and a method for producing such a semiconductor device, comprises a control gate, a first... | 11/12/2002 |
| 6462375 | Scalable dual-bit flash memory cell and its contactless flash memory array A scalable dual-bit flash memory cell of the present invention comprises a scalable gate region having a pair of floating-gate structures with a select-gate region being formed therebetween and a planarized control/select-gate over a second gate-dielectri... | 10/08/2002 |
| 6458658 | Control of floating gate oxide growth by use of an oxygen barrier When more than one bit of data are being stored in each memory cell of a flash EEPROM, more than two ranges (states) of some parameter such as cell current are defined. Since all such ranges must be fit into an available total range that is finite, an inc... | 10/01/2002 |
| 6437396 | Nonvolatile memory A structure and a process of a nonvolatile memory are provided. By forming a oxide/nitride/oxide (ONO) layer in a floating gate thin oxide (FLOTOX) memory, the same data can be programmed in one nonvolatile memory to guarantee the reliability but without ... | 08/20/2002 |
| 6438027 | Nonvolatile memory, cell array thereof, and method for sensing data therefrom Nonvolatile memory, cell array thereof, and method for sensing a data therefrom, the method including the steps of: selecting a flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and ... | 08/20/2002 |
| 6420231 | Processing techniques for making a dual floating gate EEPROM cell array An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floa... | 07/16/2002 |
| 6420237 | Method of manufacturing twin bit cell flash memory device The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1-x Gex | 07/16/2002 |
| 6417049 | Split gate flash cell for multiple storage In this invention polysilicon sidewalls on a semiconductor substrate are used as split gate flash memory cells. The sidewalls are formed around a core of silicon nitride and left standing once the silicon nitride is removed. Bit lines are implanted into t... | 07/09/2002 |
| 6351411 | Memory using insulator traps A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density o... | 02/26/2002 |
| 6339006 | Flash EEPROM cell and method of manufacturing the same The invention relates to a flash EEPROM cell and method of manufacturing the same. The method of manufacturing a flash EEPROM cell includes sequentially forming a tunnel oxide film, a polysilicon layer for a floating gate and a hard mask layer on a semico... | 01/15/2002 |
| 6333214 | Memory of multilevel quantum dot structure and method for fabricating the same A semiconductor memory having a multilevel quantum dot structure is formed by alternatively disposing conductive layers and insulation layers, and processing these layers so that quantum dots are formed in the conductive layers. The writing and reading of... | 12/25/2001 |
| 6330184 | Method of operating a semiconductor device A method of operating a semiconductor device that includes a first memory cell with discontinuous storage elements or dots (108) in lieu of a conventional floating gate can be programmed to at least one of three different states. The different states are ... | 12/11/2001 |
| 6329687 | Two bit flash cell with two floating gate regions The method of fabricating the semi-conductor device includes forming a center dielectric region on a substrate. The center dielectric region has a first thickness and the substrate includes a first conductive material. Then, a first plurality of spacers i... | 12/11/2001 |
| 6323088 | Dual floating gate programmable read only memory cell structure and method for its fabrication an operation A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while active doped regions (source and drain ... | 11/27/2001 |
| 6320784 | Memory cell and method for programming thereof A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12) a control electrode (19), and doped discontinuous storage elem... | 11/20/2001 |
| 6320216 | Memory device with barrier portions having defined capacitance It is made possible to conduct writing and erasing information at high speed with a low gate voltage, to attain high integration with reduced power dissipation and to retain information accurately. A barrier layer, a transition layer, a barrier layer, a t... | 11/20/2001 |
