Class 257/E29.306 - Hot carrier injection from channel (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E29.305. This subclass
No. of patents: 459
Last issue date: 08/12/2008

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Number	Title	Issue Date
7411246	Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby A method of forming an array of floating gate memory cells, and an array formed thereby, that includes source and drain regions formed in a substrate, and a conductive block of material disposed over the source region. The floating gate is formed as a thin, L-shaped...	08/12/2008
6703659	Low voltage programmable and erasable flash EEPROM A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlyi...	03/09/2004
6693010	Split gate memory cell with a floating gate in the corner of a trench A memory cell and method for making a memory cell. The memory cell has a floating gate and a control gate, and a source region and a drain region. The structure of the device is such that the area of capacitive coupling between the floating gate and the s...	02/17/2004
6667214	Non-volatile semiconductor memory devices and methods for manufacturing the same Examples including non-volatile semiconductor memory devices in which digitized image data and voice data can be more efficiently written and read, and methods for manufacturing the same, are described. In one example, a non-volatile semiconductor memory ...	12/23/2003
6667508	Nonvolatile memory having a split gate A novel structure of nonvolatile memory is formed on p type silicon and includes a stacked gate, a tunneling dielectric layer, a floating gate (FG), a dielectric layer and a control gate (CG). One side of the stacked gate has a source region and the other...	12/23/2003
6653183	Single-poly EPROM and method for forming the same A single-poly EPROM and method for forming the same. The single-poly EPROM has an isolation region disposed in a substrate to define a striped active area. A deep n-well is located under the isolation region and the striped active area. A gate oxide layer...	11/25/2003
6649972	Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping A programmable, read only memory device includes two diffusion areas in a substrate and a channel formed therebetween, an oxide-nitride-oxide (ONO) layer comprising a first oxide layer overlaid by a nitride layer overlaid by a second oxide layer, the nitr...	11/18/2003
6649475	Method of forming twin-spacer gate flash device and the structure of the same The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric laye...	11/18/2003
6646924	Non-volatile memory and operating method thereof A non-volatile memory is described, which comprises a plurality of memory cells, a plurality of word lines, a plurality of drain lines and a plurality of source lines. Two adjacent memory cells in the same row share a source and are grouped into a cell pa...	11/11/2003
6646923	Methods of operating semiconductor memory devices having split gate-type non-volatile memory cells Methods of operating non-volatile memory cells (e.g., EEPROM devices) include the use of negative substrate biases during programming and erasing operations. Theses methods include the step of erasing the memory cell by withdrawing negative charge from a ...	11/11/2003
6642572	Nonvolatile semiconductor memory device and method for fabricating the same A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electr...	11/04/2003
6630708	Non-volatile memory and method for fabricating the same A non-volatile memory includes a substrate: a floating gate electrode and a control gate electrode formed on the substrate; and an active layer formed around the control gate and the floating gate. The active layer has source and drain and a channel layer...	10/07/2003
6631087	Low voltage single poly deep sub-micron flash eeprom An EEPROM memory cell comprising a transistor on a first conductivity type semiconductor substrate and a capacitor formed on a second conductivity type semiconductor substrate. The capacitor comprises first and second injector regions of third conductivit...	10/07/2003
6627943	Flash memory device and method for fabricating the same A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width inc...	09/30/2003
6627947	Compact single-poly two transistor EEPROM cell A non-volatile memory cell at least partially formed in a semiconductor substrate. The cell comprises a first transistor comprising a high voltage NMOS transistor having a first active region and a second active region; a second transistor sharing said se...	09/30/2003
6627962	Semiconductor memory A semiconductor memory and its manufacturing method enable high-integrated memory cell to be realized easily. The semiconductor memory according to the present invention has an impurity diffusion region with a second conductive type that is opposite to a ...	09/30/2003
6621116	Enhanced EPROM structures with accentuated hot electron generation regions An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively ...	09/16/2003
6621115	Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface p...	09/16/2003
6617637	Electrically erasable programmable logic device An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a fl...	09/09/2003
6596585	Method of manufacturing semiconductor device Described is a semiconductor device having a silicon oxide (SiO2) film into which nitrogen atoms, in a range between approximately 2×1020 atoms/cm3 or more and 2×1021 atoms/cm3 or less, are introduc...	07/22/2003
6574143	Memory device using hot charge carrier converters A flash memory cell is based on a floating gate transistor design in which a floating gate is separated from a channel by a tunnel oxide. The cell is programmed and erased by electrons tunnelling on and off the floating gate through the tunnel oxide. To r...	06/03/2003
6574144	Flash memory with nanocrystalline silicon film coating gate A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductiv...	06/03/2003
6570790	Highly compact EPROM and flash EEPROM devices Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangemen...	05/27/2003
6566705	Enhanced EPROM structures with accentuated hot electron generation regions An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively ...	05/20/2003
6563733	Memory array architectures based on a triple-polysilicon source-side injection non-volatile memory cell A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells al...	05/13/2003
6544845	Methods of fabricating nonvolatile memory devices including bird's beak oxide A nonvolatile memory device which suppress a drain coupling by minimizing an overlap capacitance between a floating gate and a drain. The nonvolatile memory device includes a cell array region in which a plurality of memory cells are two-dimensionally arr...	04/08/2003
6545312	Nonvolatile semiconductor memory device and method for fabricating the same A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electr...	04/08/2003
6541815	High-density dual-cell flash memory structure A 2F2 flash memory cell structure and a method of fabricating the same are provided. The 2F2 flash memory cell structure includes a Si-containing substrate having a plurality of trenches formed therein. Each trench has sidewalls that...	04/01/2003
6538275	Nonvolatile semiconductor memory device and method for fabricating the same A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed thereb...	03/25/2003
6531734	Self-aligned split-gate flash memory cell having an integrated source-side erase structure and its contactless flash memory arrays A self-aligned split-gate flash memory cell of the present invention comprises an integrated floating-gate layer being at least formed on a first gate-dielectric layer having a first intergate-dielectric layer formed on its top and a second intergate-diel...	03/11/2003
6528843	Self-aligned split-gate flash memory cell having a single-side tip-shaped floating-gate structure and its contactless flash memory arrays A self-aligned split-gate flash memory cell of the present invention comprises a planarized control/select-gate conductive layer having a portion formed at least on a second gate-dielectric layer and another portion formed at least on a single-side tip-sh...	03/04/2003
6528845	Non-volatile semiconductor memory cell utilizing trapped charge generated by channel-initiated secondary electron injection The present invention provides a semiconductor device that comprises a tub region located in a semiconductor substrate, wherein the tub region has a tub electrical contact connected thereto. The semiconductor device further comprises a trap charge insulat...	03/04/2003
6525965	One-sided floating-gate memory cell Floating-gate memory cells having a control gate for coupling to a word line, a floating gate, a first source/drain region for coupling to a bit line, and a floating second source/drain region are adapted for use in flash memory devices. Such floating-gat...	02/25/2003
6521495	Method of fabricating a non-volatile memory device A non-volatile memory device and a fabrication method thereof, wherein the non-volatile memory device includes first and second memory cells in a region of a semiconductor substrate where a word line crosses a bit line. Thus, one word line can control the...	02/18/2003
6521944	Split gate memory cell with a floating gate in the corner of a trench A memory cell and method for making a memory cell. The memory cell has a floating gate and a control gate, and a source region and a drain region. The structure of the device is such that the area of capacitive coupling between the floating gate and the s...	02/18/2003
6518110	Method of fabricating memory cell structure of flash memory having annular floating gate The present invention relates to a memory cell structure of a flash memory and a method for fabricating the same and, more particularly, to a flash memory having annular floating gates. The present invention uses the capacitance coupling between the sourc...	02/11/2003
6518122	Low voltage programmable and erasable flash EEPROM A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlyi...	02/11/2003
6512700	Non-volatile memory cell having channel initiated secondary electron injection programming mechanism A non-volatile memory cell and associated cell array and memory device having reduced program disturb, improved retention of programmed information, and reduced power consumption are disclosed. The memory cell includes a control device coupled to a switch...	01/28/2003
6509603	P-channel EEPROM and flash EEPROM devices A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilic...	01/21/2003
6507066	Highly reliable flash memory structure with halo source A method of forming a Flash EEPROM device with a gate electrode stack includes forming a tunnel oxide layer, a floating gate electrode layer, a dielectric layer, and a control gate layer on a doped silicon semiconductor substrate. Then form source/drain r...	01/14/2003

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Class 257/E29.306 - Hot carrier injection from channel (EPO)