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| Number | Title | Issue Date |
| 7411246 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby A method of forming an array of floating gate memory cells, and an array formed thereby, that includes source and drain regions formed in a substrate, and a conductive block of material disposed over the source region. The floating gate is formed as a thin, L-shaped... | 08/12/2008 |
| 7365388 | Embedded trap direct tunnel non-volatile memory The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric consta... | 04/29/2008 |
| 7365389 | Memory cell having enhanced high-K dielectric A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory... | 04/29/2008 |
| 7358560 | Flash memory device and method of manufacturing the same A non-volatile memory device includes a semiconductor substrate having an active region defined by isolation films that extend along a first direction. A control gate line extends along in a second direction perpendicular to the first direction. First and second flo... | 04/15/2008 |
| 7358558 | Flash memory device A floating gate of a flash memory device is formed in a moat formed in an isolation film. Therefore, an electric field applied between a control gate and a channel region upon cycling can be precluded or mitigated. A distance between the control gate and the channel... | 04/15/2008 |
| 7342277 | Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric materia... | 03/11/2008 |
| 7339229 | Nonvolatile memory solution using single-poly pFlash technology A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the ... | 03/04/2008 |
| 7332768 | Non-volatile memory devices Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, program... | 02/19/2008 |
| 7314798 | Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the tr... | 01/01/2008 |
| 7300844 | Method of forming gate of flash memory device A method of forming a gate of a flash memory device, including the steps of forming a tunnel oxide film and a first polysilicon layer in an active region of a semiconductor substrate, an isolation film in the field region, a dielectric layer, a second polysilicon la... | 11/27/2007 |
| 7291882 | Programmable and erasable digital switch device and fabrication method and operating method thereof A programmable and erasable digital switch device is provided. An N-type memory transistor and a P-type memory transistor are formed over a substrate. The N-type memory transistor includes a first N-type doped region, a second N-type doped region, a first charge sto... | 11/06/2007 |
| 7279737 | Nonvolatile semiconductor memory device and method of manufacturing the same A nonvolatile semiconductor memory device includes a gate electrode portion composed of a floating gate electrode formed above a main surface of a semiconductor substrate of a first conductivity type via a tunnel insulating film, an inter-electrode insulating film f... | 10/09/2007 |
| 7208376 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate and pointed channel region A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface... | 04/24/2007 |
| 7205601 | FinFET split gate EEPROM structure and method of its fabrication A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in... | 04/17/2007 |
| 7170131 | Flash memory array with increased coupling between floating and control gates Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control ... | 01/30/2007 |
| 6703662 | Semiconductor device and manufacturing method thereof A semiconductor device comprises a memory cell transistor and a select transistor. An N-type first diffusion layer area is formed below side walls formed on the sides of the memory cell transistor. An N-type second diffusion layer area is formed in an are... | 03/09/2004 |
| 6700159 | Semiconductor device comprising trench-isolated transistors The present invention provides a highly reliable semiconductor device including a silicon substrate, floating gate electrodes with side walls formed on first surface of silicon substrate with a gate insulator film disposed therebetween, first and second s... | 03/02/2004 |
| 6690059 | Nanocrystal electron device A MOS transistor having utility as a charge storage device, as in a nonvolatile memory device, or as an amplifier, using the charge storage feature of the device as a way to modulate the conductivity of a channel between source and drain electrodes. Over ... | 02/10/2004 |
| 6680508 | Vertical floating gate transistor A floating gate transistor has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The ... | 01/20/2004 |
| 6680225 | Method for manufacturing a semiconductor memory The method for manufacturing a Semiconductor Memory according to the present invention comprises a step for forming a gate insulator film on the surface of a semiconductor substrate; a step for forming a mask layer having a through-hole provided in the po... | 01/20/2004 |
| 6680505 | Semiconductor storage element A nonvolatile semiconductor storage element which has a charge stored layer as a floating gate, and whose storage time is made sufficiently long. The storage element comprises a channel region formed between a source region and a drain region; first and s... | 01/20/2004 |
| 6677198 | Structure of a low-voltage channel write/erase flash memory cell and fabricating method thereof The present invention relates to a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, which structure comprises an N-substrate, a deep P-well formed on the substrate, and an N-well formed on the deep P-well.... | 01/13/2004 |
| 6674119 | Non-volatile semiconductor memory device and semiconductor integrated circuit A non-volatile semiconductor memory device includes a p-type Si substrate, an n-type well formed in the Si substrate, a control gate of a p-type buried diffusion region formed in the n-type well, an active region formed in the Si substrate in the vicinity... | 01/06/2004 |
| 6667201 | Method for manufacturing flash memory cell The present invention discloses a method for manufacturing a flash memory cell having a horizontal surrounding gate (HSG). The flash memory cell of the present invention is formed on a trench of an isolation region, and a channel of the flash memory cell ... | 12/23/2003 |
| 6660589 | Semiconductor devices and methods for fabricating the same Semiconductor devices and methods for fabricating the same include a device isolation layer formed at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. The device furth... | 12/09/2003 |
| 6645812 | Method for fabricating a non-volatile semiconductor memory cell with a separate tunnel window A method for producing a non-volatile semiconductor memory cell with a separate tunnel window cell includes the step of forming a tunnel zone in a late implantation step by performing a tunnel implantation with the aid of a tunnel window cell as a mask. T... | 11/11/2003 |
| 6642110 | Flash memory cell and method of manufacturing the same There is disclosed a flash memory cell and method of manufacturing the same, in which the circular hole is formed in the insulating film formed on the silicon substrate, the floating gate having a cylindrical shape is formed within the hole and the contro... | 11/04/2003 |
| 6639269 | Electrically programmable memory cell configuration and method for fabricating it A memory cell contains a planar transistor whose channel region is disposed at a bottom of a depression in a substrate. A floating gate electrode of the transistor adjoins the bottom of the depression, the bottom being provided with a first dielectric dis... | 10/28/2003 |
| 6639835 | Static NVRAM with ultra thin tunnel oxides Structures and methods involving non volatile depletion mode p-channel memory cells with an ultrathin tunnel oxide thicknesses, e.g. less than 50 Å, have been provided. Both the write and erase operations are performed by tunneling and method embodiments... | 10/28/2003 |
| 6630381 | Preventing dielectric thickening over a floating gate area of a transistor A process for a memory transistor (e.g. flash-EEPROM cell), which includes forming an isolation-spacer between a control gate and an erase line of over a floating gate by first growing a thin thermal oxide to be in contact with the first sidewall of contr... | 10/07/2003 |
| 6627945 | Memory device and method of making A non-volatile memory device includes a number of memory cells, parts of which are delineated by insulators. The insulators each include both a lower trench-fill insulator portion in a trench in the substrate, and an upper protruding portion that protrude... | 09/30/2003 |
| 6624028 | Method of fabricating poly spacer gate structure The present invention provides a fabrication method of devices like flash memory cells, which is used to fabricate a poly spacer as a floating gate. In the present invention, an oxide, a predefined and patterned first dielectric, a first poly silicon, and... | 09/23/2003 |
| 6624029 | Method of fabricating a self-aligned non-volatile memory cell Disclosed is a self-aligned non-volatile memory cell comprising a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate ... | 09/23/2003 |
| 6621130 | Semiconductor device and an electronic device The present invention provides a semiconductor nonvolatile memory in which writing or erasing of storing information can be carried out at a high speed with low consumption power and in which dispersion width of a threshold voltage after writing or erasin... | 09/16/2003 |
| 6621733 | Segmented bit line EEPROM page architecture An EEPROM segment bit line page memory array includes a plurality of bit lines extending in a Y-direction; a plurality of word lines extending in an X-direction; a plurality of sub-bit lines extending in the Y-direction; a plurality of segment select word... | 09/16/2003 |
| 6617639 | Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling A floating gate flash memory device including a substrate comprising a source region, a drain region, and a channel region positioned therebetween; a floating gate electrode positioned above the channel region and separated from the channel region by a tu... | 09/09/2003 |
| 6614071 | Non-volatile semiconductor memory device A semiconductor memory device of the present invention comprises, a semiconductor substrate, a drain region formed in the semiconductor substrate, a source region formed in the semiconductor substrate, a gate insulating film formed between the drain regio... | 09/02/2003 |
| 6600188 | EEPROM with a neutralized doping at tunnel window edge An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. P-type lightly-doped drain regions are located at the polysilicon edges of the tunnel window. During the p... | 07/29/2003 |
| 6596588 | Method of fabricating a flash memory cell A semiconductor substrate has a V-shape structure positioned in the semiconductor substrate. A first ion implantation process is then performed to form a first doping region around the V-shape structure in the semiconductor substrate. Following this, a fi... | 07/22/2003 |
| 6590260 | Memory device having improved programmability A method for enhancing the operating characteristics of memory devices (400C), such as flash memory devices, by manipulating the Fermi energy levels of the substrate (406) and the floating gate (404). In so doing, the gap between the minimum conduction ba... | 07/08/2003 |
