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| Number | Title | Issue Date |
| 7368341 | Semiconductor circuit arrangement with trench isolation and fabrication method An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor layer (14). The trench simultaneously fulfils a multiplicity of functions, namely an insula... | 05/06/2008 |
| 7244986 | Two-bit cell semiconductor memory device A 2-bit cell is made up of first and second diffusion regions provided on a substrate surface, first and second storage nodes adjacent to the first and second diffusion region, first and second gate electrodes provided on first and second storage nodes, a third stor... | 07/17/2007 |
| 6800885 | Asymmetrical double gate or all-around gate MOSFET devices and methods for making same An asymmetric double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a first fin formed on a substrate; a second fin formed on the substrate; a first gate formed adjacent first sides of the first and second fins, the first gate being doped w... | 10/05/2004 |
| 6700155 | Charge trapping device and method for implementing a transistor having a configurable threshold A device and method uses charge trapping to configure and adjust a threshold voltage (Vt) for a field effect transistor (FET). The charge trapping mechanism can be controlled by bias voltages applied to the FET, so that rapid/dynamic changes can be made t... | 03/02/2004 |
| 6693027 | Method for configuring a device to include a negative differential resistance (NDR) characteristic A process for forming/configuring a device to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is implemented by incorporating a dynamic threshold voltage in such device. An onset poi... | 02/17/2004 |
| 6690030 | Semiconductor device with negative differential resistance characteristics A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or "thinned" at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon o... | 02/10/2004 |
| 6686267 | Method for fabricating a dual mode FET and logic circuit having negative differential resistance mode A process for forming a dual mode FET and a logic circuit to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is selectively enabled/disabled by forming a body contact bias, thus perm... | 02/03/2004 |
| 6686240 | Semiconductor memory device having a multiple tunnel junction layer pattern and method of fabricating the same A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunn... | 02/03/2004 |
| 6686623 | Nonvolatile memory and electronic apparatus An active region, a source region, and a drain region are formed on a single crystal semiconductor substrate or a single crystal semiconductor thin film. Impurity regions called pinning regions are formed in striped form in the active region so as to reac... | 02/03/2004 |
| 6680245 | Method for making both a negative differential resistance (NDR) device and a non-NDR device using a common MOS process A semiconductor manufacturing process is disclosed that is suitable for making both negative differential resistance (NDR) and non-NDR devices at the same time. An NDR process is thus integrated within a conventional CMOS process so that compatibility wit... | 01/20/2004 |
| 6677204 | Multigate semiconductor device with vertical channel current and method of fabrication The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first ch... | 01/13/2004 |
| 6673674 | Method of manufacturing a semiconductor device having a T-shaped floating gate In a semiconductor device having a plurality of memory cells, each of the memory cells includes a floating gate, a control gate, a source and drain, and a silicide layer. The floating gate is formed on a semiconductor substrate of a first conductivity typ... | 01/06/2004 |
| 6674109 | Nonvolatile memory An object of the invention is to decrease leakage current of a nonvolatile memory and to design improvement of memory characteristic thereof. The invention is characterized by comprising an FET of MFMIS structure having metal layer (M) and insulation laye... | 01/06/2004 |
| 6670243 | Method of making a flash memory device with an inverted tapered floating gate In a semiconductor memory device such as a flash memory, a field oxide film is formed to a forward taper shape on a semiconductor substrate, and a floating gate is formed to a reverse (inverted) taper shape between the field oxide film over the semiconduc... | 12/30/2003 |
| 6664601 | Method of orperating a dual mode FET & logic circuit having negative differential resistance mode A process for operating a dual mode FET and a logic circuit to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is selectively enabled/disabled by biasing a body contact, thus permitt... | 12/16/2003 |
| 6657250 | Vertical flash memory cell with buried source rail A non-volatile memory cell has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The ... | 12/02/2003 |
| 6657252 | FinFET CMOS with NVRAM capability The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having Non-Volatile Random Access Memory (NVRAM) capability. NVRAM capability arises from the presence of double floating gates arr... | 12/02/2003 |
| 6654284 | Channel write/erase flash memory cell and its manufacturing method A pseudo-dynamic operating method and a flash memory cell capable of performing this operating method are disclosed. A parasitic capacitor near the drain terminal of the flash memory can be charged in few microseconds during operation. Interference genera... | 11/25/2003 |
| 6642106 | Method for increasing core gain in flash memory device using strained silicon A method of memory device fabrication. In one embodiment, the method of memory device (400) fabrication comprises implanting an element (200) in a substrate (440). The element (200) causes an inherent elongational realignment of atoms in silicon (101,102)... | 11/04/2003 |
| 6639268 | Flash memory with ultra thin vertical body transistors Structures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating gate transistor includes a pillar extending outwardly from... | 10/28/2003 |
| 6635921 | Semiconductor memory device having a multiple tunnel junction layer pattern and method of fabricating the same A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunn... | 10/21/2003 |
| 6635530 | Methods of forming gated semiconductor assemblies The invention includes a method of forming a gated semiconductor assembly. A first transistor gate layer is formed over a substrate. A silicon nitride layer is formed over the first transistor gate layer. The silicon nitride layer comprises a first portio... | 10/21/2003 |
| 6627944 | Floating gate memory device using composite molecular material A floating gate memory device has a floating gate and an insulating layer on the floating gate. A control gate is on the insulating layer. The insulating layer is made up of a molecular matrix with ionic complexes distributed in the molecular matrix. By t... | 09/30/2003 |
| 6597034 | Non-volatile memory and semiconductor device A non-volatile memory comprising a semiconductor active layer provided on an insulating substrate, an insulating film provided on the semiconductor active layer, a floating gate electrode provided on the insulating film, an anodic oxidized film obtained b... | 07/22/2003 |
| 6596617 | CMOS compatible process for making a tunable negative differential resistance (NDR) device A method of making an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. By implanting ions into... | 07/22/2003 |
| 6594193 | Charge pump for negative differential resistance transistor An integrated circuit device includes a charge pump for providing a bias signal to a field effect transistor (FET) that is capable of operating in a negative differential resistance mode. The bias signal is applied to a gate of the NDR FET to control the ... | 07/15/2003 |
| 6570790 | Highly compact EPROM and flash EEPROM devices Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangemen... | 05/27/2003 |
| 6559470 | Negative differential resistance field effect transistor (NDR-FET) and circuits using the same An improved negative differential resistance field effect transistor (NDR-FET) is disclosed. The NDR FET includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation l... | 05/06/2003 |
| 6525377 | Low threshold voltage MOS transistor and method of manufacture A low threshold voltage MOS device on a semiconductor substrate is disclosed. The substrate has an upper surface, and a first well region is disposed in said semiconductor substrate extending downwardly from the semiconductor substrate upper surface. The ... | 02/25/2003 |
| 6525379 | Memory device, method of manufacturing the same, and integrated circuit Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in b... | 02/25/2003 |
| 6524911 | Combination of BPTEOS oxide film with CMP and RTA to achieve good data retention An improved method of fabricating a non-volatile semiconductor device having a BPTEOS oxide film is provided. The present method utilizes the step of performing a RTA at a temperature of about 800° C. immediately after the deposition of the BPTEOS film s... | 02/25/2003 |
| 6518589 | Dual mode FET & logic circuit having negative differential resistance mode An electronic device includes a FET that is capable of operating in a negative differential resistance mode as well as in a conventional FET mode. The selection of the mode can be accomplished by providing a control signal to a body terminal of the FET as... | 02/11/2003 |
| 6512274 | CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. For a fixed gate voltage, the MISFET chann... | 01/28/2003 |
| 6509602 | Nonvolatile memory and manufacturing method thereof Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ioniz... | 01/21/2003 |
| 6504762 | Highly compact EPROM and flash EEPROM devices Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangemen... | 01/07/2003 |
| 6503797 | Nonvolatile semiconductor storage apparatus and production method of the same The present invention prevents a charge-up during a wiring layer etching in a nonvolatile semiconductor storage apparatus, having a floating gate and a control gate to which both of positive and negative voltages are applied during a memory cell operation... | 01/07/2003 |
| 6501685 | Channel write/erase flash memory cell and its manufacturing method A pseudo-dynamic operating method and a flash memory cell capable of performing this operating method are disclosed. A parasitic capacitor near the drain terminal of the flash memory can be charged in few microseconds during operation. Interference genera... | 12/31/2002 |
| 6501126 | Semiconductor structure and procedure for minimizing non-idealities The invention relates to a semiconductor structure and a method for minimizing non-idealities in a semiconductor structure, in which a drain; a source, a floating gate (102) and at least one input (108) capacitively connected'to the floating gate (102) ar... | 12/31/2002 |
| 6479862 | Charge trapping device and method for implementing a transistor having a negative differential resistance mode A charge trapping structure for use with an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) is disclosed. A dielectric layer is formed close to a channel region of the MISFET, and includes a number of trapping sites which are arra... | 11/12/2002 |
| 6472684 | Nonvolatile memory and manufacturing method thereof Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ioniz... | 10/29/2002 |
