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| Number | Title | Issue Date |
| 7413955 | Transistor for memory device and method for manufacturing the same Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a gro... | 08/19/2008 |
| 7400489 | System and a method of driving a parallel-plate variable micro-electromechanical capacitor A method of driving a parallel-plate variable micro-electromechanical capacitor includes establishing a first charge differential across first and second conductive plates of a variable capacitor in which the first and second conductive plates are separated by a var... | 07/15/2008 |
| 7378692 | Integrated electronic circuit comprising superposed components An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed wi... | 05/27/2008 |
| 7358142 | Method for forming a FinFET by a damascene process A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and ... | 04/15/2008 |
| 7352037 | Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug ... | 04/01/2008 |
| 7312504 | Transistor for memory device and method for manufacturing the same Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a gro... | 12/25/2007 |
| 7274053 | Fin device with capacitor integrated under gate electrode A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator c... | 09/25/2007 |
| 7229867 | Process for producing a field-effect transistor and transistor thus obtained A substrate supporting a portion of a semiconductor material is used to produce a field-effect transistor. A portion of a temporary material lies between the portion of semiconductor material and the substrate. A gate is formed, which comprises an upper part in rigi... | 06/12/2007 |
| 7211858 | Split gate storage device including a horizontal first gate and a vertical second gate in a trench A split gate memory cell can include a first gate electrode and a second gate electrode. The split gate memory cell can also include a first diffusion region underlying a trench in a semiconductor substrate, wherein the trench has a sidewall, and the first diffusion... | 05/01/2007 |
| 7187042 | Backgated FinFET having different oxide thicknesses A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thickne... | 03/06/2007 |
| 7183597 | Quantum wire gate device and method of making same The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The m... | 02/27/2007 |
| 7176092 | Gate electrode for a semiconductor fin device A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and... | 02/13/2007 |
| 7154119 | Thin film transistor with plural channels and corresponding plural overlapping electrodes An object of the present invention is to provide a technique for improving characteristics of a TFT and realizing the structure of the TFT optimal for driving conditions of a pixel section and a driving circuit, using a smaller number of photo masks. A semiconductor... | 12/26/2006 |
| 7141854 | Double-gated silicon-on-insulator (SOI) transistors with corner rounding A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patt... | 11/28/2006 |
| 7135707 | Semiconductor device having insulated gate electrode An insulated-gate field effect transistor with the structure capable of weakening an electric field near or around the drain thereof. To this end, the transistor of the top gate type has its gate electrode which is formed of two kinds of metal layers (4, 5) c... | 11/14/2006 |
| 6927435 | Semiconductor device and its production process A semiconductor device comprising a semiconductor substrate, gate insulators formed on the substrate, and gate electrodes formed on the gate insulators, the gate insulators which are mainly composed of a material selected from titanium oxide, zirconium oxide and haf... | 08/09/2005 |
| 6906344 | Thin film transistor with plural channels and corresponding plural overlapping electrodes An object of the present invention is to provide a technique for improving characteristics of a TFT and realizing the structure of the TFT optimal for driving conditions of a pixel section and a driving circuit, using a smaller number of photo masks. A semiconductor... | 06/14/2005 |
| 6700134 | Semiconductor device provided with semiconductor circuit consisting of semiconductor element and method of manufacturing the same The present invention provides a semiconductor device and a method of manufacturing the same, the device being provided with a semiconductor circuit consisting of a semiconductor element that is capable of improving characteristics of a TFT and has unifor... | 03/02/2004 |
| 6696309 | Methods for making electrooptical device and driving substrate therefor An electrooptical device including a first substrate including a display section having pixel electrodes and a peripheral-driving-circuit section provided on a periphery of the display section, a second substrate, and an optical material disposed between ... | 02/24/2004 |
| 6693258 | Process for producing thin film semiconductor device and laser irradiation apparatus A polycrystalline thin film of good quality is obtained by improving a crystallization process of a semiconductor thin film using laser light. After conducting a film forming step of forming a non-single crystal semiconductor thin film on a surface of a s... | 02/17/2004 |
| 6689650 | Fin field effect transistor with self-aligned gate The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion j... | 02/10/2004 |
| 6689649 | Methods of forming transistors An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each cond... | 02/10/2004 |
| 6686630 | Damascene double-gate MOSFET structure and its fabrication method The present invention provides a method for fabricating sub-0.05 μm double-gated MOSFET devices utilizing a damascene-gate process. The damascene-gate process provides sub-0.05 μm double-gated MOSFET devices which include a frontside poly gate electrode... | 02/03/2004 |
| 6680487 | Semiconductor comprising a TFT provided on a substrate having an insulating surface and method of fabricating the same There is disclosed a semiconductor device and a method of fabricating the semiconductor device in which a heat time required for crystal growth is shortened and a process is simplified. Two catalytic element introduction regions are arranged at both sides... | 01/20/2004 |
| 6677644 | Semiconductor integrated circuit having low voltage and high voltage transistors An integrated circuit formed on a SOI substrate has a low withstand voltage MOS transistors formed in the SOI substrate and comprising source and drain regions formed in the semiconductor film of the SOI substrate, a gate insulating film formed over the s... | 01/13/2004 |
| 6673661 | Self-aligned method for forming dual gate thin film transistor (TFT) device A method for fabricating a dual gate thin film transistor (TFT) device provides for forming a pair of source/drain layers self-aligned with respect to a first gate electrode and forming a second gate electrode self-aligned with respect to both the pair of... | 01/06/2004 |
| 6664598 | Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-g... | 12/16/2003 |
| 6664582 | Fin memory cell and method of fabrication The present invention provides a memory cell and method for forming the same that results in improved cell density without overly increasing fabrication cost and complexity. The preferred embodiment of the present invention provides a fin design to form t... | 12/16/2003 |
| 6660596 | Double planar gated SOI MOSFET structure A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographic... | 12/09/2003 |
| 6657259 | Multiple-plane FinFET CMOS The present invention provides FinFETs on the same substrate utilizing various crystal planes for FET current channels in order to optimize mobility and/or to reduce mobility. An embodiment of the present invention provides a substrate having a surface or... | 12/02/2003 |
| 6653657 | Semiconductor device and a method of manufacturing the same To provide a TFT that can operate at a high speed by forming a crystalline semiconductor film while controlling the position and the size of a crystal grain in the film to use the crystalline semiconductor film for a channel forming region of the TFT. Ins... | 11/25/2003 |
| 6653221 | Method of forming a ground in SOI structures An SOI device structure is provided which facilitates mitigation of charge build up caused by floating body effects. A ground contact is formed from a top insulating layer to a bottom silicon layer. The ground contact extends through the insulating layer,... | 11/25/2003 |
| 6649979 | Method of manufacturing MOSFET and structure thereof A method of manufacturing an MOSFET. A substrate is provided. A trench filled with an insulating layer is formed in the substrate. The upper portion of the insulating layer is removed and then a spacer is formed on the side-wall of the trench. A sacrifici... | 11/18/2003 |
| 6645797 | Method for forming fins in a FinFET device using sacrificial carbon layer A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mas... | 11/11/2003 |
| 6646307 | MOSFET having a double gate A double gate MOSFET. The MOSFET includes a bottom gate electrode and a bottom gate dielectric disposed over the bottom gate electrode. A semiconductor body region is disposed over the bottom gate dielectric and the bottom gate electrode, and disposed bet... | 11/11/2003 |
| 6645826 | Semiconductor device and method of fabricating the same In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semicon... | 11/11/2003 |
| 6645795 | Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator Steep concentration gradients are achieved in semiconductor device of small sizes formed on SOI or double SOI wafers by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain bou... | 11/11/2003 |
| 6642090 | Fin FET devices from bulk semiconductor and method for forming The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET ... | 11/04/2003 |
| 6642115 | Double-gate FET with planarized surfaces and self-aligned silicides It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit comprising a first gate, a second gate, and source and drain regions adjacent the first and second gates, wherein the structure has a planar u... | 11/04/2003 |
| 6642591 | Field-effect transistor A field-effect transistor includes a silicon substrate on which is formed a channel region, a source region and a drain region. A gate insulation layer of a transition metal oxide having a perovskite structure is formed over at least the channel region, a... | 11/04/2003 |
