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| Number | Title | Issue Date |
| 7271447 | Semiconductor device A semiconductor substrate includes a first semiconductor layer that is formed on a semiconductor base substrate, a second semiconductor layer that is formed on the first semiconductor layer and that has an etching selection ratio smaller than that of the first semic... | 09/18/2007 |
| 7081391 | Integrated circuit devices having buried insulation layers and methods of forming the same An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate... | 07/25/2006 |
| 6703688 | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p... | 03/09/2004 |
| 6677192 | Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p... | 01/13/2004 |
| 6674131 | Semiconductor power device for high-temperature applications In a SiC substrate (10), a first active region (12) composed of n-type heavily doped layers (12a) and undoped layers (12b), which are alternately stacked, and a second active region (13) composed of p-type heavily doped layers (13a) and undoped layers (13... | 01/06/2004 |
| 6646322 | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p... | 11/11/2003 |
| 6642581 | Semiconductor device comprising buried channel region A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gat... | 11/04/2003 |
| 6638825 | Method for fabricating a high voltage device A high voltage device and a method for fabricating the same are disclosed, which improves voltage-resistant characteristics to protect against high voltage applied to a gate electrode. The high voltage device includes a semiconductor substrate having firs... | 10/28/2003 |
| 6621125 | Buried channel device structure A buried channel device structure for an electrostatic discharge protection circuit capable of minimizing the effect on the electrostatic discharge protection circuit due to current flowing close to gate oxide layer. A p+ ion-doped region is formed above ... | 09/16/2003 |
| 6617640 | Field-effect-controllable semiconductor configuration with a laterally extending channel zone A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first conductivity type, a channel zone of the first conductivity type, and at least one control electro... | 09/09/2003 |
| 6617653 | MISFET P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type he... | 09/09/2003 |
| 6610366 | Method of N2O annealing an oxide layer on a silicon carbide layer Methods for fabricating a layer of oxide on a silicon carbide layer are provided by forming the oxide layer on the silicon carbide layer and then annealing the oxide layer in an N2 O environment at a predetermined temperature profile and at a p... | 08/26/2003 |
| 6593191 | Buried channel strained silicon FET using a supply layer created through ion implantation A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supp... | 07/15/2003 |
| 6555839 | Buried channel strained silicon FET using a supply layer created through ion implantation A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or burie... | 04/29/2003 |
| 6555872 | Trench gate fermi-threshold field effect transistors Field effect transistors include a semiconductor substrate of first conductivity type having a surface. A tub region of second conductivity type is in the semiconductor substrate at the surface and extends into the semiconductor substrate a first depth fr... | 04/29/2003 |
| 6518623 | Semiconductor device having a buried-channel MOS structure A gate electrode is buried in a trench formed in the main surface of a semiconductor substrate and faces a counter doped layer, and source/drain layers are formed on both sides of the trench. Thus the source/drain layers are formed in shallower areas than... | 02/11/2003 |
| 6469347 | Buried-channel semiconductor device, and manufacturing method thereof MOS type semiconductor device is formed on the primary surface of a semiconductor substrate. A channel region includes a punch-through stopper layer, a lower counter-doped layer, and an upper counter-doped layer. The punch-through stopper layer is formed ... | 10/22/2002 |
| 6365473 | Method of manufacturing a transistor in a semiconductor device There is disclosed a method of manufacturing a transistor in a semiconductor device by which, when forming an elevated channel using an epitaxy technology for further expanding the applied region of a buried channel PMOS transistor, indium ions having the... | 04/02/2002 |
| 6271093 | Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETs Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sen... | 08/07/2001 |
| 6245607 | Buried channel quasi-unipolar transistor A buried channel lateral quasi-unipolar transistor having low flicker or 1/f noise has a bulk region that forms the base of the buried quasi-unipolar transistor. A drain region is implanted into the bulk region to form a drain/collector. A source region i... | 06/12/2001 |
| 6246093 | Hybrid surface/buried-channel MOSFET A MOSFET having a buried channel structure and an adjacent surface channel structure between a source region and a drain region. The surface channel structure is preferably formed adjacent the source region via angular implantation techniques. By combinin... | 06/12/2001 |
| 6246077 | Semiconductor device A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type formed on the surface of the first semiconductor layer, the energy difference between the bottom of the c... | 06/12/2001 |
| 6232642 | Semiconductor device having impurity region locally at an end of channel formation region There is provided a semiconductor device having a novel structure in which high reliability and high field effect mobility can be simultaneously achieved. In an insulated gate transistor formed on a single crystal silicon substrate, pinning regions 105 an... | 05/15/2001 |
| 6229188 | MOS field effect transistor and its manufacturing method The present invention provides novel structures of MOS field effect transistor which operate with high speed and low power consumption. This has been achieved through providing epitaxial growth layers on a substrate of high impurity doping concentration i... | 05/08/2001 |
| 6228725 | Semiconductor devices with pocket implant and counter doping A low power transistor (70, 70') formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a ga... | 05/08/2001 |
| 6200864 | Method of asymmetrically doping a region beneath a gate A method of asymmetrically doping a region beneath a gate by controlling the lateral surface profile of the gate using a mask. A first embodiment of the method includes forming a mask over the gate such that it extends beyond the opposing sides of the gat... | 03/13/2001 |
| 6171895 | Fabrication of buried channel devices with shallow junction depth The channel doping profile of a PMOS field effect transistor consists of a shallow distribution of a P-type dopant as a threshold adjust implant, a deeper distribution of an N-type dopant as an buried channel stop implant and a still deeper implantation o... | 01/09/2001 |
| 6147383 | LDD buried channel field effect semiconductor device and manufacturing method An LDD-structured field-effect semiconductor device that can eliminate fluctuations in the threshold voltage caused by variations in the position of higher-density diffusion layers, thereby suppressing variations in the threshold voltage to a lower level.... | 11/14/2000 |
| 6133587 | Silicon carbide semiconductor device and process for manufacturing same A n- -type source region 5 is formed on a predetermined region of the surface layer section of the p-type silicon carbide semiconductor layer 3 of a semiconductor substrate 4. A low-resistance p-type silicon carbide region 6 is formed on a pred... | 10/17/2000 |
| 6111296 | MOSFET with plural channels for punch through and threshold voltage control Impurity regions shaped in linear patterns are formed in parallel with the channel direction (electric field direction) in a channel forming region. The impurity regions restrain the expansion of the drain side depletion layer, and the narrow channel effe... | 08/29/2000 |
| 6103580 | Method to form ultra-shallow buried-channel MOSFETs A method to form buried channel MOSFETs in an integrated circuit is described. Field oxide isolation regions overlying a semiconductor substrate are provided. The surface of the substrate in the active device regions is cleaned. A doped silicate glass lay... | 08/15/2000 |
| 6081011 | CMOS logic gate having buried channel NMOS transistor for semiconductor devices and fabrication method of the same A CMOS logic gate for a semiconductor apparatus having a buried channel NMOS transistor and a fabrication method of the same are disclosed. The CMOS logic gate according to the present invention includes a pull up unit gate-connected by an input voltage a... | 06/27/2000 |
| 6051482 | Method for manufacturing buried-channel PMOS A method for manufacturing a buried-channel pMOSFET device that utilizes a plasma doping technique to form a very shallow P-type channel layer on the top surface of a sub-micron buried-channel pMOSFET. The buried-channel pMOSFET device formed by the metho... | 04/18/2000 |
| 5998854 | Semiconductor device A semiconductor device has a transistor made of a semiconductor which has a source and drain regions, a channel region, a gate insulative film, and a gate electrode. The gate electrode is connected to a part of the channel region. The channel region has t... | 12/07/1999 |
| 5986312 | Field effect semiconductor device having improved connections In a field effect semiconductor device, in order to increase the operation speed and to make the device finer by lowering the sheet resistance, and to lower the production cost by reducing the process steps, the diffusion layer 17 is surrounded by SiO | 11/16/1999 |
| 5977564 | Semiconductor device A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type formed on the surface of the first semiconductor layer, the energy difference between the bottom of the c... | 11/02/1999 |
| 5969385 | Ultra-low power-delay product NNN/PPP logic devices Transistors have source, drain and channel regions all of the same conductivity type. The channel region is very thin, not more than about 500 Å and preferably about 300 Å or even 100 Å in thickness. A very thin oxide layer having a thickness of much l... | 10/19/1999 |
| 5933737 | Buried-channel MOS transistor and process of producing same In fabricating a buried p-channel MOS transistor using an n-type substrate, a shallow n-type diffused layer is formed by ion implantation in each of intended source and drain regions so as to become oppositely adjacent to the shallow p-type diffused layer... | 08/03/1999 |
| 5923985 | MOS field effect transistor and its manufacturing method A method of manufacturing a MOS field effect transistor comprises forming on a semiconductor substrate a first epitaxial growth layer having an impurity doping concentration lower than that of the semiconductor substrate, forming on the first epitaxial gr... | 07/13/1999 |
| 5885876 | Methods of fabricating short channel fermi-threshold field effect transistors including drain field termination region A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as a result of drain bias. The drain field terminating region preven... | 03/23/1999 |
