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A pizza mold for forming a plurality of concentric raised ridges of dough (i.e., crust) on the surface of a pizza pie.
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| Number | Title | Issue Date |
| 7420241 | Semiconductor memory device and method of manufacturing the same A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gat... | 09/02/2008 |
| 7355245 | Structure for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extend... | 04/08/2008 |
| 7227227 | Reduced leakage semiconductor device The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th... | 06/05/2007 |
| 7112844 | Semiconductor device and manufacturing method thereof The objectives of the present invention are achieving TFTs having a small off current and TFT structures optimal for the driving conditions of a pixel portion and driver circuits, and providing a technique of making the differently structured TFTs without increasing... | 09/26/2006 |
| 6700176 | MOSFET anti-fuse structure and method for making same An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain ex... | 03/02/2004 |
| 6680224 | Methods of forming and operating field effect transistors having gate and sub-gate electrodes Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the chan... | 01/20/2004 |
| 6646462 | Extraction of drain junction overlap with the gate and the channel length for ultra-small CMOS devices with ultra-thin gate oxides The present invention generally relates to a method of determining a source/drain junction overlap and a channel length of a small device, such as a MOS transistor. A large reference device having a known channel length is provided, and a source, drain, a... | 11/11/2003 |
| 6593623 | Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (5... | 07/15/2003 |
| 6514824 | Semiconductor device with a pair of transistors having dual work function gate electrodes Techniques are described for fabricating a pair of ଲ-identical transistors, in other words, a pair of transistors whose dimensions and electrical characteristics, other than their respective gate electrode work functions, are substantially similar. ... | 02/04/2003 |
| 6468843 | MIS semiconductor device having an LDD structure and a manufacturing method therefor It is intended to provide a method of forming a gate overlap lightly doped impurity region (GOLD). After a gate insulating film is formed by a material mainly made of silicon oxide and a gate electrode is formed with, for instance, silicon, lightly doped ... | 10/22/2002 |
| 6461924 | MOS transistor for high-speed and high-performance operation and manufacturing method thereof A MOS transistor of the present invention includes a semiconductor substrate of a first conductivity type impurity, a gate insulating layer formed on the semiconductor substrate, gate electrodes formed on the gate insulating layer, and an oxide layer form... | 10/08/2002 |
| 6407436 | Semiconductor device with abrupt source/drain extensions with controllable gate electrode overlap A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spa... | 06/18/2002 |
| 6359310 | Shallow doped junctions with a variable profile gradation of dopants Disclosed is an electrical device including a process for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention comprises, first providing and masking a surface on an in-process integra... | 03/19/2002 |
| 6300207 | Depleted sidewall-poly LDD transistor The present invention is directed to a metal oxide semiconductor transistor having a fully overlapped lightly doped drain (LDD) structure which offers the advantages of conventional fully overlapped LDD transistors but which significantly reduces the drai... | 10/09/2001 |
| 6284577 | MIS semiconductor device having an LDD structure and a manufacturing method therefor It is intended to provide a method of forming a gate overlap lightly doped impurity region (GOLD). After a gate insulating film is formed by a material mainly made of silicon oxide and a gate electrode is formed with, for instance, silicon, lightly doped ... | 09/04/2001 |
| 6284613 | Method for forming a T-gate for better salicidation A method for a T-gate and salicide process that allows narrow bottom gate widths below 0.25 μm and wide top gate widths to allow silicide gate contacts on the top of the T-gate. A dummy gate composed of an insulating material is formed over the substrate... | 09/04/2001 |
| 6277699 | Method for forming a metal-oxide-semiconductor transistor A method for forming a MOS transistor is provided. A gate oxide layer, a polysilicon layer, a barrier layer and a conductive layer are sequentially formed on a provided substrate. A photolithography and etching process is carried out to remove a portion o... | 08/21/2001 |
| 6274446 | Method for fabricating abrupt source/drain extensions with controllable gate electrode overlap A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spa... | 08/14/2001 |
| 6274906 | MOS transistor for high-speed and high-performance operation and manufacturing method thereof A MOS transistor of the present invention includes a semiconductor substrate of a first conductivity type impurity, a gate insulating layer formed on the semiconductor substrate, gate electrodes formed on the gate insulating layer, and an oxide layer form... | 08/14/2001 |
| 6268640 | Forming steep lateral doping distribution at source/drain junctions A semiconductor device is fabricated by implanting into a semiconductor substrate non-doping ions at a tilt angle of at least about 10° to laterally extend preamorphization of the substrate portion and then implanting into the substrate dopants for provi... | 07/31/2001 |
| 6211555 | Semiconductor device with a pair of transistors having dual work function gate electrodes Techniques are described for fabricating a pair of ଲ-identical transistors, in other words, a pair of transistors whose dimensions and electrical characteristics, other than their respective gate electrode work functions, are substantially similar. ... | 04/03/2001 |
| 6207997 | Thin film transistor for antistatic circuit and method for fabricating the same A thin film transistor for an antistatic circuit includes: wells formed on a silicon substrate; insulating layers for electrical isolation between electrodes formed within the wells; low density impurity diffused regions respectively interposed between th... | 03/27/2001 |
| 6180471 | Method of fabricating high voltage semiconductor device A method of fabricating a high voltage semiconductor device. A semiconductor substrate doped with a first type dopant and comprising a gate is provided. A cap oxide layer is formed on the gate optionally. A first ion implantation with a light second type ... | 01/30/2001 |
| 6169315 | Metal oxide semiconductor field effect transistor (MOSFET) and method for making thereof A metal oxide semiconductor field effect transistor includes source and drain regions formed between a gate. The gate comprises a first conductive layer and a second conductive layer formed on the first conductive layer, and the second conductive layer ha... | 01/02/2001 |
| 6124174 | Spacer structure as transistor gate A semiconductor process includes forming a spacer support structure on an upper surface of a semiconductor substrate. The semiconductor substrate includes a channel region that is laterally displaced between first and second source/drain regions. A. The s... | 09/26/2000 |
| 6091118 | Semiconductor device having reduced overlap capacitance and method of manufacture thereof A semiconductor device and process for manufacture thereof is disclosed in which a gate electrode with reduced overlap capacitance is formed by forming a gate electrode on a surface of a semiconductor and doping edge portions of the gate electrode with a ... | 07/18/2000 |
| 6071825 | Fully overlapped nitride-etch defined device and processing sequence The present invention relates to methods for fabricating Fully Overlapped Nitride-Etch Defined (Fond) devices. These methods permit the lateral dimension and depth of the lowly-doped source and drain extensions to be independently controlled and well defi... | 06/06/2000 |
| 6037630 | Semiconductor device with gate electrode portion and method of manufacturing the same A first polysilicon film which contains phosphorus as an impurity is formed on a semiconductor substrate. A second polysilicon film which is higher in phosphorus concentration than the first polysilicon film is formed on the first polysilicon film. The se... | 03/14/2000 |
| 5977591 | High-voltage-resistant MOS transistor, and corresponding manufacturing process A MOS transistor capable of withstanding relatively high voltages is of a type integrated on a region included in a substrate of semiconductor material, having conductivity of a first type and comprising a channel region intermediate between a first activ... | 11/02/1999 |
| 5970353 | Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (5... | 10/19/1999 |
| 5920104 | Reducing reverse short-channel effect with light dose of P with high dose of as in n-channel LDD Submicron nLDD CMOS logic devices with improved current drive and reduced reverse short-channel effects having heavily doped As and lightly doped P nLDD region.... | 07/06/1999 |
| 5918134 | Method of reducing transistor channel length with oxidation inhibiting spacers A method of fabricating a transistor. A dielectric layer is formed on an upper surface of a semiconductor substrate. A photoresist layer is then deposited on a dielectric layer and patterned with a photolithography exposure device to expose a region of th... | 06/29/1999 |
| 5912492 | Integrated circuit structure incorporating a metal oxide semiconductor field effect transistor (MOSFET) having improved hot carrier immunity A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) exhibiting enhanced immunity to Hot Carrier Effects (HCEs), and a method by which the MOSFET may be formed. To form the MOSFET there is first provided a semiconductor substrate having a gate die... | 06/15/1999 |
| 5897363 | Shallow junction formation using multiple implant sources Disclosed is a process for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention comprises, first providing and masking a surface on an in-process integrated circuit wafer on which the ... | 04/27/1999 |
| 5891792 | ESD device protection structure and process with high tilt angle GE implant A structure and method for fabricating an ESD device for FET transistors by forming a silicon germanium region 40 under a channel region 44 of a field effect transistor (FET). The silicon germanium region 40 comprises the base of a parasitic bipolar 200 t... | 04/06/1999 |
| 5879995 | High-voltage transistor and manufacturing method therefor A fourth impurity region having a smaller junction depth than that of the second impurity region, and having a third impurity concentration which is lower than that of the second impurity region is formed between the first impurity region and second impur... | 03/09/1999 |
| 5879999 | Method of manufacturing an insulated gate semiconductor device having a spacer extension An insulated gate semiconductor device (10) having a gate structure (45) that includes a conductive spacer (32) and an extension region (46) extending from the conductive spacer (32). To form the gate structure (45), a stack having sidewalls (22) is forme... | 03/09/1999 |
| 5869374 | Method to form mosfet with an inverse T-shaped air-gap gate structure A method for fabricating a MOS transistor with an inverse T-shaped air-gap gate structure on a semiconductor substrate is disclosed. The T-shaped air-gap gate structure reduces the parasitic resistance and capacitance; hence device structure operation spe... | 02/09/1999 |
| 5851861 | MIS semiconductor device having an LDD structure and a manufacturing method therefor It is intended to provide a method of forming a gate overlap lightly doped impurity region (GOLD). After a gate insulating film is formed by a material mainly made of silicon oxide and a gate electrode is formed with, for instance, silicon, lightly doped ... | 12/22/1998 |
| 5837588 | Method for forming a semiconductor device with an inverse-T gate lightly-doped drain structure A method for forming an ultra-short channel device with an inverse-T gate lightly-doped drain (ITLDD) structure is disclosed. The method includes forming a silicon layer (14) over a semiconductor substrate (10), and forming a dielectric layer (16) on the ... | 11/17/1998 |
