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| Number | Title | Issue Date |
| 7400016 | Semiconductor device realizing characteristics like a SOI MOSFET In a semiconductor device, source/drain layers have a low resistivity region and an extension region extending from the low resistivity region toward the channel region. The extension regions are lower in impurity concentration and shallower in depth than the low re... | 07/15/2008 |
| 7326619 | Method of manufacturing integrated circuit device including recessed channel transistor A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device iso... | 02/05/2008 |
| 7253481 | High performance MOS device with graded silicide A semiconductor device suffering fewer current crowding effects and a method of forming the same are provided. The semiconductor device includes a substrate, a gate over the substrate, a gate spacer along an edge of the gate and overlying a portion of the substrate,... | 08/07/2007 |
| 7154146 | Dielectric plug in mosfets to suppress short-channel effects The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices including a MOSFET having a dielectric plug. The dielectric plug is fabricated by forming an oxide layer over... | 12/26/2006 |
| 6693026 | Semiconductor device and method for fabricating the same A semiconductor device is disclosed, which can extend an effective channel length without changing layout. The semiconductor device includes a device barrier film formed in a semiconductor substrate, for defining an active region, a channel region formed ... | 02/17/2004 |
| 6690070 | Insulated gate semiconductor device and its manufacturing method A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. ... | 02/10/2004 |
| 6686626 | Source-down power transistor The invention relates to a source-down power transistor, in which narrow trenches filled with insulated polysilicon are provided between a source pillar and a drain pillar. Inversion channels form on the side walls of the trenches when a positive drain vo... | 02/03/2004 |
| 6670694 | Semiconductor device A surface orientation other than a (100) surface orientation is exposed to the surface portion of a silicon substrate having the (100) surface orientation, for example. A silicon epitaxial growth layer is formed only on a region containing a channel formi... | 12/30/2003 |
| 6664163 | Low on-resistance trench lateral MISFET with better switching characteristics and method for manufacturing same A high-voltage and low on-resistance semiconductor device incorporates a trench structure that provides improved switching characteristics. In a preferred embodiment, a Trench Lateral Power MISFET is provided having a gate, channel and drift regions that ... | 12/16/2003 |
| 6657263 | MOS transistors having dual gates and self-aligned interconnect contact windows A method of fabricating an IC device on a substrate comprising MOS transistors and other IC components. Each of the transistors of the IC device comprises a raised source electrode, a raised drain electrode, dual gate electrodes and self-aligned interconn... | 12/02/2003 |
| 6656845 | Method for forming semiconductor substrate with convex shaped active region Within a method for fabricating a semiconductor substrate while employing formed thereover a mask layer there is first employed the mask layer as an etch mask layer for forming a pair of isolation trenches within the semiconductor substrate and then later... | 12/02/2003 |
| 6652808 | Methods for the electronic assembly and fabrication of devices Methods provide for electric field assisted self-assembly of functionalized programmable nucleic acids, nucleic acid modified structures, and other selective affinity or binding moieties as building blocks for: creating molecular electronic and photonic m... | 11/25/2003 |
| 6649481 | Methods of fabricating a semiconductor device structure for manufacturing high-density and high-performance integrated-circuits The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned mann... | 11/18/2003 |
| 6649455 | SOI type MOS element and manufacturing method thereof To present a SOI type MOS element excellent in yield, performance and characteristic, easy in manufacture, and low in cost, and a method of manufacturing the same. A SOI type MOS transistor structure comprising polysilicon electrodes 128 for gate, source ... | 11/18/2003 |
| 6649479 | Method for fabricating MOSFET device A MOSFET device includes a gate formed on a multi-surface area of a semiconductor substrate formed of a first surface which is not etched, a second surface etched in parallel with the first surface, and a surface connecting the first and second surfaces. ... | 11/18/2003 |
| 6642130 | Method for fabricating highly integrated transistor A method for fabricating a transistor comprises steps of forming a conductive well region, an isolation oxide layer, a first pad oxide layer, a conductive LDD (low doped drain) region and a source/drain region on a silicon substrate. A pad nitride layer i... | 11/04/2003 |
| 6638825 | Method for fabricating a high voltage device A high voltage device and a method for fabricating the same are disclosed, which improves voltage-resistant characteristics to protect against high voltage applied to a gate electrode. The high voltage device includes a semiconductor substrate having firs... | 10/28/2003 |
| 6638482 | Reconfigurable detection and analysis apparatus and method Methods and apparatus for use of a stacked, reconfigurable system is provided. The stacked, reconfigurable system includes an inlet for receipt of a sample, a first chamber defined by a bottom support, an intermediate member, and a first spacer, the first... | 10/28/2003 |
| 6630394 | System for reducing silicon-consumption through selective deposition Disclosed is a system for fabricating a semiconductor device (100). A layer of cobalt (32) is deposited onto a silicon region (104, 106, 108) and annealed to form a cobalt silicide layer (118, 120, 122). Silicon layers (124, 126, 128) are selectively depo... | 10/07/2003 |
| 6621131 | Semiconductor transistor having a stressed channel A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and... | 09/16/2003 |
| 6621118 | MOSFET, semiconductor device using the same and production process therefor A MOSFET includes: a first conductivity type a semiconductor substrate having a trench formed in a surface area thereof, a gate electrode formed on the semiconductor substrate; and a trench gate electrode which is adjacent to the gate electrode and is bur... | 09/16/2003 |
| 6617654 | Semiconductor device with sidewall spacers and elevated source/drain region Source and drain regions include regions of an epitaxial silicon film on the surface of the substrate and regions in the substrate. The depth of junctions of the source and drain regions is identical to or shallower than the depth of junctions of extensio... | 09/09/2003 |
| 6614079 | All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS A complementary metal oxide semiconductor (CMOS) device having silicide contacts that are self-aligned to deep junction edges formed within a surface of a semiconductor substrate as well as a method of manufacturing the same are disclosed. Specifically, t... | 09/02/2003 |
| 6579765 | Metal oxide semiconductor field effect transistors A method of fabricating a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device with an elevated source 29 and drain 30. A MOSFET region is defined on the surface of a silicon substrate 18, and a central area of that region removed by etching ... | 06/17/2003 |
| 6566208 | Method to form elevated source/drain using poly spacer A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly do... | 05/20/2003 |
| 6566216 | Method of manufacturing a trench transistor To provide a semiconductor device and a process for manufacturing the same which is capable of suppressing short channel effect and preventing a current from leaking between a contact and a silicon substrate. The semiconductor device of the present invent... | 05/20/2003 |
| 6562707 | Method of forming a semiconductor device using selective epitaxial growth A method of forming a semiconductor device using selective epitaxial growth (SEG) is provided. This method includes forming an insulating layer pattern having a window on a semiconductor substrate. The window exposes a predetermined region of the semicond... | 05/13/2003 |
| 6555438 | Method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions A method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions is described. A gate structure having a gate insulating layer, a first conductive layer and a first dielectric layer is formed on a substrat... | 04/29/2003 |
| 6555425 | Method for manufacturing transistor A method of manufacturing a transistor. The method comprising the steps of providing a substrate. The substrate comprises a gate oxide layer formed thereon, a polysilicon layer formed on the gate oxide layer, an offset spacer formed on a sidewall of the p... | 04/29/2003 |
| 6548875 | Sub-tenth micron misfet with source and drain layers formed over source and drains, sloping away from the gate A semiconductor device having a low channel resistance without degrading transistor characteristics even for the 0.1 μm generation or later, and also: a manufacturing method of the device. The method includes fabricating source/drain electrodes and a gat... | 04/15/2003 |
| 6534823 | Semiconductor device A semiconductor body has source and drain regions (4 and 5; 4' and 5') spaced apart by a body region (6; 6') and a drain drift region (50; 50') and both meeting the same surface (3a) of the semiconductor body. An insulated gate structure (7; 70'; 700) is ... | 03/18/2003 |
| 6534370 | Method for fabricating a semiconductor device having an elevated source/drain scheme The present invention is a method for fabricating a semiconductor device having an elevated source/drain scheme which includes the steps of: forming a first photoresist film on a top surface of a semiconductor substrate; forming a second photoresist film ... | 03/18/2003 |
| 6531781 | Fabrication of transistor having elevated source-drain and metal silicide A method of forming a transistor, the method comprises following steps: provides a substrate; covers part of the substrate by a doped amorphous silicon layer and covers part of the substrate by a first dielectric layer; forms a metal silicide layer on the... | 03/11/2003 |
| 6531410 | Intrinsic dual gate oxide MOSFET using a damascene gate process Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as... | 03/11/2003 |
| 6528855 | MOSFET having a low aspect ratio between the gate and the source/drain A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitanc... | 03/04/2003 |
| 6528847 | Metal oxide semiconductor device having contoured channel region and elevated source and drain regions A metal oxide semiconductor (MOS) device includes a silicon substrate, source and drain regions having a predetermined junction depth (dj) relative to the surface of the silicon substrate, and a gate region having a contoured channel region for... | 03/04/2003 |
| 6521946 | Electrostatic discharge resistant extended drain metal oxide semiconductor transistor A semiconductor device comprising a first transistor (40) and a second transistor (100), both formed in a semiconductor substrate (50). The first transistor comprises a gate conductor (56) and a gate insulator (54) separating the gate conductor from a sem... | 02/18/2003 |
| 6518625 | Semiconductor device An n-type impurity layer is formed on a boundary portion between a source/drain and a field oxide film in a portion deeper than the source/drain. Even if a metal silicide layer such as a Co silicide layer extends into a portion under the field oxide film ... | 02/11/2003 |
| 6518129 | Manufacture of trench-gate semiconductor devices The manufacture of a trench-gate semiconductor device, for example a power transistor or a memory device includes the steps of forming at a surface (10a) of a semiconductor body (10) a first mask (51) having a first window (51a), providing a thin layer of... | 02/11/2003 |
| 6518623 | Semiconductor device having a buried-channel MOS structure A gate electrode is buried in a trench formed in the main surface of a semiconductor substrate and faces a counter doped layer, and source/drain layers are formed on both sides of the trench. Thus the source/drain layers are formed in shallower areas than... | 02/11/2003 |
