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| Number | Title | Issue Date |
| 7417266 | MOSFET having a JFET embedded as a body diode A field effect transistor, in accordance with one embodiment, includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode. ... | 08/26/2008 |
| 7378688 | Method and apparatus for a low noise JFET device on a standard CMOS process A microelectric product and the method for manufacturing the product are provided. A source and drain are spaced from one another in a first direction and are connected to opposing ends of a channel to provide a set voltage. First and second gates are spaced from on... | 05/27/2008 |
| 7335928 | Semiconductor device having a metal conductor in ohmic contact with the gate region on the bottom of each the first groove A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel betwee... | 02/26/2008 |
| 7335952 | Semiconductor device and manufacturing method therefor To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method fo... | 02/26/2008 |
| 7307329 | Electronic device with guard ring An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the substrate, an active layer arranged within the opening on the surface of the substrate, the active layer... | 12/11/2007 |
| 7304335 | Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performance and high scaling down density A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel... | 12/04/2007 |
| 7268394 | JFET structure for integrated circuit and fabrication method Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alte... | 09/11/2007 |
| 7226818 | High performance field effect transistors comprising carbon nanotubes fabricated using solution based processing The present invention is directed toward field effect transistors (FETs) and thin film transistors (TFTs) comprising carbon nanotubes (CNTs) and to methods of making such devices using solution-based processing techniques, wherein the CNTs within such devices have b... | 06/05/2007 |
| 6661056 | DMOS transistor protected against polarity reversal The present invention relates to a circuit configuration for protecting against polarity reversal of a DMOS transistor. A charge carrier zone (30) is provided, situated in the drift zone (14) of DMOS transistor (10), made up of individual partial charge carrie... | 12/09/2003 |
| 6639277 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 10/28/2003 |
| 6633065 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 10/14/2003 |
| 6613616 | Method for fabricating field-effect transistors in integrated semiconductor circuits and integrated semiconductor circuit fabricated with a field-effect transistor of this type including a dual gate A method for fabricating a field-effect transistor situated within an integrated semiconductor circuit. At least two gate regions each extending between a source region and a drain region and are disposed such that they lie one above the other in a thickn... | 09/02/2003 |
| 6614088 | Breakdown improvement method and sturcture for lateral DMOS device In a lateral DMOS device 10 breakdown voltage is controlled by a voltage divider 50 coupled at opposite ends to the source 18 and drain 19. The divider node N1 between first and second resistive elements R1, R2 is connected to a second level conductive sh... | 09/02/2003 |
| 6600192 | Vertical field-effect semiconductor device with buried gate region A buried gate region, a buried gate contact region and a gate contact region are provided on an SiC substrate. Thereby, a depletion layer expands in the channel region, and a high withstand voltage is attained in the normally off state. By applying a volt... | 07/29/2003 |
| 6580137 | Damascene double gated transistors and related manufacturing methods This invention provides the structure and fabrication process of a completely planar, Damascene double gated transistor. The structure has a novel self-aligned, hyper-abrupt retrograde body and a zero-parasitic, endwall gate-body connection. The structure... | 06/17/2003 |
| 6552393 | Power MOS transistor having increased drain current path A power MOS transistor that permits a large current to flow without a broad gate width being employed. The power MOS transistor includes a substrate of a first conductivity type; a well region of a second conductivity type; a first electrode region whose ... | 04/22/2003 |
| 6316296 | Field-effect transistor and method of manufacturing same A dual gate structure field-effect transistor is manufactured by forming a trench in an SOI substrate comprised of a semiconductor support substrate, a buried insulation layer formed on the support substrate and an SOI semiconductor layer formed on the in... | 11/13/2001 |
| 6291242 | Methods for generating polynucleotides having desired characteristics by iterative selection and recombination A method for DNA reassembly after random fragmentation, and its application to mutagenesis of nucleic acid sequences by in vitro or in vivo recombination is described. In particular, a method for the production of nucleic acid fragments or polynucleotides... | 09/18/2001 |
| 6288429 | Semiconductor device A semiconductor device which materializes dynamic threshold operation, on the assumption of the application of a bulk semiconductor substrate. The semiconductor substrate has a first conductivity type well region (11), a source region (12) and a drain reg... | 09/11/2001 |
| 6262451 | Electrode structure for transistors, non-volatile memories and the like An electrode structure for semiconductor devices includes first electrode material positioned in overlying relationship to the surface of a substrate so as to define a first side wall perpendicular thereto. A nonconductive side wall spacer is formed on th... | 07/17/2001 |
| 6236070 | MES/MIS FET Disclosed is an improved field effect transistor (FET) employing both a metal-semiconductor (MES) gate and a metal-insulator-semiconductor (MIS) gate, which FET is particularly useful to provide amplification at microwave frequencies. The use of the MIS g... | 05/22/2001 |
| 6005267 | MES/MIS FET with split-gate RF input Disclosed is an improved field effect transistor (FET) employing both a metal-semiconductor (MES) gate and a metal-insulator-semiconductor (MIS) gate, which FET is particularly useful to provide amplification at microwave frequencies. The use of the MIS g... | 12/21/1999 |
| 5877049 | Method for forming advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back ... | 03/02/1999 |
| 5793055 | Hybrid electronic devices, particularly Josephson transistors A step junction is provided for superconductor/semiconductor heterostructure hybrid devices like tunneling transistors, in a body of p-InAs with a vertical side connecting the low plateau and high plateau on which superconductors, preferably of niobium, a... | 08/11/1998 |
| 5780912 | Asymmetric low power MOS devices Low threshold voltage MOS devices having asymmetric halo implants are disclosed herein. An asymmetric halo implant provides a pocket region located under a device's source or drain near where the source (or drain) edge abuts the device's channel region. T... | 07/14/1998 |
| 5773863 | Low power, high performance junction transistor An improved junction transistor requiring low power and having high performance is described. The transistor includes a substrate, a well region of a first conductivity type, and source and drain regions of a second conductivity type separated by a channe... | 06/30/1998 |
| 5622880 | Method of making a low power, high performance junction transistor Low threshold voltage MOS devices having buried electrodes are disclosed herein. Such devices have source and drain regions which include tip regions and plug regions. The buried electrodes have bottom boundaries located above the bottoms of the plug regi... | 04/22/1997 |
| 5608253 | Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back ... | 03/04/1997 |
| 5581100 | Trench depletion MOSFET A vertical trench power MOS transistor with low on-resistance is obtained by eliminating the inversion region of a conventional structure. In one embodiment, a deep-depletion region is formed between the trench gates to provide forward blocking capability... | 12/03/1996 |
| 5576245 | Method of making vertical current flow field effect transistor A transistor constructed in accordance with our invention includes an N+ substrate, an N- region formed on the N+ substrate, a P- body region formed on the N- region, and an N+ source region formed on the P- body region. A vertical groove extends through ... | 11/19/1996 |
| 5432377 | Dielectrically isolated semiconductor device and a method for its manufacture A semiconductor device is supported by a semiconductor body which comprises a substrate, an oxide layer and a weakly doped monocrystalline wafer. Trenches for a dielectrically isolating layer which surrounds a component region are etched in the wafer. A f... | 07/11/1995 |
| 5396085 | Silicon carbide switching device with rectifying-gate A silicon carbide switching device includes a three-terminal interconnected silicon MOSFET and silicon carbide MESFET (or JFET) in a composite substrate of silicon and silicon carbide. For three terminal operation, the gate electrode of the silicon carbid... | 03/07/1995 |
| 5296727 | Double gate FET and process for manufacturing same A high speed and highly functional MOSFET having a thin channel formed in a single crystalline layer is controlled by voltages applied to both an upper gate electrode and a buried gate layer that sandwich the channel therebetween.... | 03/22/1994 |
| 5164325 | Method of making a vertical current flow field effect transistor A transistor constructed in accordance with our invention includes an N+ substrate, an N- region formed on the N+ substrate, a P- body region formed on the N- region, and an N+ source region formed on the P- body region. A vertical groove extends through ... | 11/17/1992 |
| 5065132 | Programmable resistor and an array of the same A programmable resistor 10 is provided having a resistive element 12. Resistive element 12 includes a substrate 26 formed by a layer of semiconductor of a first conductivity-type. A current path 32 is formed in substrate 26 by a layer of semiconductor of ... | 11/12/1991 |
| 4835586 | Dual-gate high density fet A dual-gate vertical field effect transistor comprises an N+ substrate (102) which serves as a drain, and N-epitaxial layer (104) formed on the N+ substrate, and an N+ layer (106) formed at the surface of the epitaxial layer which serves as a source. A pl... | 05/30/1989 |
| 4823173 | High voltage lateral MOS structure with depleted top gate region The present invention provides an improved lateral drift region for both bipolar and MOS devices where improved breakdown voltage and low ON resistance are desired. A top gate of the same conductivity type as the device region with which it is associated ... | 04/18/1989 |
| 4791462 | Dense vertical j-MOS transistor A j-MOS structure is disclosed which operates at high current densities and provides high current handling capability. A heavily doped N+ substrate, acting as a drain, has grown on it a lightly doped N- epitaxial layer. Within the epitaxial layer are mult... | 12/13/1988 |
| 4698654 | Field effect transistor with a submicron vertical structure and its production process The invention relates to a vertical field effect transistor operating under ballistic conditions at very high frequencies (100-200 GHz). In order to increase the output impedance of this transistor, as well as its power, the field effect of the first gate... | 10/06/1987 |
| 4523368 | Semiconductor devices and manufacturing methods A field effect device having a gate over a portion of a surface of a semiconductor disposed between a source region and a drain region and including a buried doped region having a conductivity type opposite the conductivity type of the semiconductor forme... | 06/18/1985 |
