"The abolishment of pain in surgery is a chimera. It is absurd to go on seeking it...knife and pain are two words in surgery that must forever be associated in the consciousness of the patient."
Dr. Alfred Velpeau, French surgeon ; 1839
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| Number | Title | Issue Date |
| 7385247 | At least penta-sided-channel type of FinFET transistor An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section tran... | 06/10/2008 |
| 7372086 | Semiconductor device including MOSFET and isolation region for isolating the MOSFET A semiconductor device comprises a semiconductor substrate, a MOSFET including a double gate structure provided on the semiconductor substrate, and an isolation region for isolating the MOSFET from other elements comprising a trench provided on the surface of the se... | 05/13/2008 |
| 7342283 | Semiconductor device An object of the present invention is to provide a semiconductor device which enables to reduce the device area, while securing the breakdown voltage between the drain and the source of each MOS transistor for the semiconductor device including plural MOS transistor... | 03/11/2008 |
| 7335945 | Multi-gate MOS transistor and method of manufacturing the same Provided are a multi-gate MOS transistor and a method of manufacturing the same. Two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin are used... | 02/26/2008 |
| 7315057 | Split gate non-volatile memory devices and methods of forming same Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming... | 01/01/2008 |
| 7262098 | Manufacturing process of a semiconductor non-volatile memory cell A process for manufacturing a non-volatile memory cell having at least one gate region, the process including the steps of depositing a first dielectric layer onto a semiconductor substrate; depositing a first semiconductor layer onto the first dielectric layer to f... | 08/28/2007 |
| 7256432 | Field-effect transistor An electric-field control electrode (5) is formed between a gate electrode (2) and a drain electrode (3). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed below the electric-field control elec... | 08/14/2007 |
| 7202517 | Multiple gate semiconductor device and method for forming same A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device. ... | 04/10/2007 |
| 7187042 | Backgated FinFET having different oxide thicknesses A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thickne... | 03/06/2007 |
| 7091566 | Dual gate FinFet A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate... | 08/15/2006 |
| 6696725 | Dual-gate MOSFET with channel potential engineering A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions... | 02/24/2004 |
| 6680224 | Methods of forming and operating field effect transistors having gate and sub-gate electrodes Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the chan... | 01/20/2004 |
| 6670673 | Semiconductor device and method for manufacturing semiconductor device A first trench is formed in a surface of an n+ -type semiconductor substrate that forms a source region. A p-type base region, an n- -type drift region, and an n+ -type drain region are deposited in this order in the first... | 12/30/2003 |
| 6661055 | Transistor in semiconductor devices The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which a voltage is applied apart from a gate electrode and forme... | 12/09/2003 |
| 6661057 | Tri-level segmented control transistor and fabrication method A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed ... | 12/09/2003 |
| 6649979 | Method of manufacturing MOSFET and structure thereof A method of manufacturing an MOSFET. A substrate is provided. A trench filled with an insulating layer is formed in the substrate. The upper portion of the insulating layer is removed and then a spacer is formed on the side-wall of the trench. A sacrifici... | 11/18/2003 |
| 6642591 | Field-effect transistor A field-effect transistor includes a silicon substrate on which is formed a channel region, a source region and a drain region. A gate insulation layer of a transition metal oxide having a perovskite structure is formed over at least the channel region, a... | 11/04/2003 |
| 6638801 | Semiconductor device and its manufacturing method A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than... | 10/28/2003 |
| 6624032 | Structure and process flow for fabrication of dual gate floating body integrated MOS transistors A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer... | 09/23/2003 |
| 6621118 | MOSFET, semiconductor device using the same and production process therefor A MOSFET includes: a first conductivity type a semiconductor substrate having a trench formed in a surface area thereof, a gate electrode formed on the semiconductor substrate; and a trench gate electrode which is adjacent to the gate electrode and is bur... | 09/16/2003 |
| 6617927 | High frequency power amplifier module, and wireless communications system A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage... | 09/09/2003 |
| 6596597 | Method of manufacturing dual gate logic devices The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. The inventive process also provides a method of selectively etching german... | 07/22/2003 |
| 6548870 | Semiconductor device In the semiconductor device, a first impurity region and a second impurity region are formed in a surface of a semiconductor substrate at a regular interval, and a gate insulating layer is formed on the semiconductor substrate between the first impurity r... | 04/15/2003 |
| 6492212 | Variable threshold voltage double gated transistors and method of fabrication The present invention provides a double gate transistor and a method for forming the same that facilitates the formation of different transistors having different threshold voltages. The embodiments of the present invention form transistors having differe... | 12/10/2002 |
| 6433639 | High frequency power amplifier module and wireless communication system A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage... | 08/13/2002 |
| 6420234 | Short channel length transistor and method of fabricating the same Transistor and method for fabricating the same, which can form a channel length shorter than a lithography limit and adjust a substrate impurity concentration variably, the method including the steps of (1) depositing an insulating film on a semiconductor... | 07/16/2002 |
| 6413825 | Method for signal processing An improved structure and method are provided for signal processing. The structure includes dual-gated metal-oxide semiconducting field effect transistor (MOSFET). The dual-gated MOSFET can be fabricated according to current CMOS processing techniques. Th... | 07/02/2002 |
| 6392271 | Structure and process flow for fabrication of dual gate floating body integrated MOS transistors A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer... | 05/21/2002 |
| 6359298 | Capacitively coupled DTMOS on SOI for multiple devices A MOSFET multiple device structure is provided. The structure comprises a plurality of MOSFET devices sharing at least one heavily doped region extending underneath a gate region of at least two of the plurality of MOSFET devices. The shared heavily doped... | 03/19/2002 |
| 6355961 | Structure and method for improved signal processing An improved structure and method are provided for signal processing. The structure includes dual-gated metal-oxide semiconducting field effect transistor (MOSFET). The dual-gated MOSFET can be fabricated according to current CMOS processing techniques. Th... | 03/12/2002 |
| 6348387 | Field effect transistor with electrically induced drain and source extensions For fabricating a field effect transistor within an active device area of a semiconductor substrate, a gate dielectric is formed on the active device area of the semiconductor substrate, and a gate structure is formed on the gate dielectric with the gate ... | 02/19/2002 |
| 6285057 | Semiconductor device combining a MOSFET structure and a vertical-channel trench-substrate field effect device A semiconductor device that provides for substrate current exiting a MOSFET structure, and hence the performance thereof, to be independently and controllably tuned. The semiconductor device includes a semiconductor substrate of a first conductivity type,... | 09/04/2001 |
| 6262451 | Electrode structure for transistors, non-volatile memories and the like An electrode structure for semiconductor devices includes first electrode material positioned in overlying relationship to the surface of a substrate so as to define a first side wall perpendicular thereto. A nonconductive side wall spacer is formed on th... | 07/17/2001 |
| 6259142 | Multiple split gate semiconductor device and fabrication method A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are elect... | 07/10/2001 |
| 6222788 | Vertical gate transistors in pass transistor logic decode circuits Systems and methods are provided for vertical gate transistors in static pass transistor decode circuits. The vertical gate transistors have multiple vertical gates which are edge defined such that only a single transistor is required for multiple logic i... | 04/24/2001 |
| 6218703 | Semiconductor device with control electrodes formed from semiconductor material A MOS semiconductor device with control electrodes for improved switching accuracy and operational speeds of the device at reduced power consumption levels. The semiconductor device includes a substrate, a source electrode region and a drain electrode reg... | 04/17/2001 |
| 6144081 | Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow tre... | 11/07/2000 |
| 6104068 | Structure and method for improved signal processing An improved structure and method are provided for signal processing. The structure includes dual-gated metal-oxide semiconducting field effect transistor (MOSFET). The dual-gated MOSFET can be fabricated according to current CMOS processing techniques. Th... | 08/15/2000 |
| 6097070 | MOSFET structure and process for low gate induced drain leakage (GILD) A structure and method for forming a metal oxide semiconductor field effect transistor structure comprises, a substrate having a gate-channel region and source and drain regions adjacent the gate-channel region, a gate insulator over the substrate, a cent... | 08/01/2000 |
| 6090693 | Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which is contacted and driven separately from the conventional gate of the transistor. The gate sp... | 07/18/2000 |