...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
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| Number | Title | Issue Date |
| 7372087 | Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage A structure for use in a static induction transistor includes a semiconductor body having first and second semiconductor layers on a substrate, with the second layer having a dopant concentration of around an order of magnitude higher than the dopant concentration o... | 05/13/2008 |
| 7187021 | Static induction transistor A transistor switch for a system operating at high frequencies is provided. The transistor switch comprises a graded channel region between a source region and a drain region, the graded channel region configured for providing a low resistance to mobile negative cha... | 03/06/2007 |
| 7164154 | Gate wiring layout for silicon-carbide-based junction field effect transistor A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a th... | 01/16/2007 |
| 6693308 | Power SiC devices having raised guard rings Silicon carbide semiconductor power devices having epitaxially grown guard rings edge termination structure are provided. Forming the claimed guard rings from an epitaxially grown SiC layer avoids the traditional problems associated with implantation of g... | 02/17/2004 |
| 6635906 | Voltage sustaining layer with opposite-doped islands for semi-conductor power devices A semiconductor high-voltage device comprising a voltage sustaining layer between a n+ -region and a p+ -region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p(or n)-islands. The effect of t... | 10/21/2003 |
| 6576929 | Silicon carbide semiconductor device and manufacturing method A channel layer 4 is formed on an n- -type epitaxial layer 2 and first gate areas 3, and field enhanced area(s) 5 and second gate areas 6 are formed on the first gate areas 3. Furthermore, n+ -type source areas 7 and a third gate are... | 06/10/2003 |
| 6498368 | Power semiconductor device In a semiconductor device having a first terminal 101 (source terminal) and a second terminal 102 (drain terminal), the substrate main surface of a semiconductor chip is on the (110) face, the main contact face of an n-type region 2 and a p-type region 4 ... | 12/24/2002 |
| 6469359 | Semiconductor device and a method for production thereof A semiconductor device of planar structure has a pn-junction (10) formed by a first layer (1) doped according to a first conductivity type, n or p, and on top thereof a second layer (2) doped according to a second conductivity type. The second layer has a... | 10/22/2002 |
| 6444527 | Method of operation of punch-through field effect transistor A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inv... | 09/03/2002 |
| 6368930 | Self aligned symmetric process and device A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base... | 04/09/2002 |
| 6255710 | 3-D smart power IC An integrated smart power circuit including a power semiconductor device fabricated on a conducting substrate with a source positioned adjacent the upper surface of the substrate, a control terminal between the upper and lower surfaces, and a drain positi... | 07/03/2001 |
| 6242794 | Self-aligned symmetric intrinsic device A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base... | 06/05/2001 |
| 6229197 | Epitaxial overgrowth method and devices A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The ... | 05/08/2001 |
| 6180959 | Static induction semiconductor device, and driving method and drive circuit thereof In a silicon carbide static induction transistor, at a surface part of a semiconductor substrate, a p-type gate region is formed partially overlapping a n-type source region, whereby the high accuracy in alignment between the gate region and the source re... | 01/30/2001 |
| 6117735 | Silicon carbide vertical FET and method for manufacturing the same In a method for forming a silicon carbide vertical FET, a first mask and a second mask that overlaps the first mask are used so that a first conductivity type impurity region is defined by one end of a certain portion of the first mask, and that portion o... | 09/12/2000 |
| 6097046 | Vertical field effect transistor and diode A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).... | 08/01/2000 |
| 6069043 | Method of making punch-through field effect transistor A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inv... | 05/30/2000 |
| 6008519 | Vertical transistor and method A vertical transistor (70) comprising a first semiconductor layer (14) of a first conductive type. A gate structure (32) of a second conductive type disposed on the first semiconductor layer (14). The gate structure (32) may include a plurality of gates (... | 12/28/1999 |
| 5962893 | Schottky tunneling device An n-semiconductor layer is arranged on a low-resistance n-substrate. A drain electrode is in ohmic contact with the n-substrate. A source electrode forms a Schottky junction with the n-semiconductor layer. A gate electrode is arranged adjacent to the sou... | 10/05/1999 |
| 5945701 | Static induction transistor A static induction transistor having source, drain and gate regions. Channel regions are defined between adjacent gates and a drift region is defined from the ends of the channel regions to the drain. The channel and drift regions have predetermined dopin... | 08/31/1999 |
| 5946572 | Method of manufacturing a semiconductor device having recessed gate structures A gate structure including semiconductor regions each having a high impurity-concentration and being formed within respective one of recessed portions provided in a surface of a first semiconductor substrate, and then a second semiconductor substrate is b... | 08/31/1999 |
| 5910665 | Low capacitance power VFET method and device A method and structure for a vertical FET transistor device (VFET) is described for a lower junction capacitance VFET to decrease the switching power loss and achieve increased current capacity and/or deceased thermal dissipation. In a preferred embodimen... | 06/08/1999 |
| 5903020 | Silicon carbide static induction transistor structure A static induction transistor having a silicon carbide substrate upon which is deposited a silicon carbide layer arrangement. The layer arrangement has a plurality of spaced gate regions for controlling current flow from a source region to a drain region ... | 05/11/1999 |
| 5894140 | Semiconductor device having recessed gate structures and method of manufacturing the same A gate structure including semiconductor regions each having a high impurity-concentration and being formed within respective one of recessed portions provided in a surface of a first semiconductor substrate, and then a second semiconductor substrate is b... | 04/13/1999 |
| 5889298 | Vertical JFET field effect transistor A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The ... | 03/30/1999 |
| 5883406 | High-speed and high-density semiconductor memory A multiplicity of field effect type semiconductor memory elements are formed perpendicular to a surface of a semiconductor wafer. Charge carriers are transported in the semiconductor bulk perpendicular to the surface and a potential barrier is formed in t... | 03/16/1999 |
| 5814548 | Process for making n-channel or p-channel permeable base transistor with a plurality layers A method for producing an electronic component with a plurality of layers fabricating in a laminated composite, comprising laterally structuring at least one of the layers having a p or n conductivity characteristic by forming one of the layers in a sieve... | 09/29/1998 |
| 5753826 | Flow meter having a vibration dampener The invention concerns a Karman's vortex flow meter including dampening members for absorbing vibrations. A stopper is provided to permit limited movement between an amplifier casing and a supporting stand containing a flow detector. The stopper is couple... | 05/19/1998 |
| 5753938 | Static-induction transistors having heterojunction gates and methods of forming same A semiconductor switching device includes a plurality of adjacent heterojunction-gate static-induction transistor (SIT) unit cells connected in parallel in a monocrystalline silicon carbide substrate having first and second opposing faces, a relatively hi... | 05/19/1998 |
| 5747842 | Epitaxial overgrowth method and devices A vertical field effect transistor (100) and fabrication method with buried gates; (104) having spaced apart gate fingers and connecting structure and overgrown with source and channel epilayer followed by a doping connection of the gate fingers and conne... | 05/05/1998 |
| 5712189 | Epitaxial overgrowth method A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The ... | 01/27/1998 |
| 5705830 | Static induction transistors A static induction transistor includes a substrate and a drift layer with different doping levels. At least two mesas are formed on the drift layer and a heavily doped region is positioned on a top surface of each of the mesas. A gate contact extends alon... | 01/06/1998 |
| 5698868 | High-speed heterojunction transistor A high-speed heterojunction transistor includes a first region for controlling current, and a second region for receiving carriers which have passed the first region. An energy level difference between a lowermost valley of energy and an upper valley of e... | 12/16/1997 |
| 5686330 | Method of making a self-aligned static induction transistor A method of fabricating self-aligned static induction transistors is disclosed. The method comprises fabricating a silicon substrate having an active area. A guard ring is formed around the active area. Source and gate regions are formed, and a self-align... | 11/11/1997 |
| 5663582 | High frequency static induction transistor having high output A recess-gate type static induction transistor having a high breakdown voltage is provided, which includes an n-type channel region provided over an n+ -type drain region, p+ -type elongated gate regions provided in grooves of the ch... | 09/02/1997 |
| 5624860 | Vertical field effect transistor and method A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The ... | 04/29/1997 |
| 5612547 | Silicon carbide static induction transistor A static induction transistor fabricated of silicon carbide, preferably 6H polytype, although any silicon carbide polytype may be used. The preferred static induction transistor is the recessed Schottky barrier gate type. Thus, a silicon carbide substrate... | 03/18/1997 |
| 5600156 | Diamond semiconductor device with P-I-N type multilayer structure A diamond semiconductor device of the present invention comprises an n-type diamond layer to which an n-type dopant is doped at high concentration so that metal conduction dominates, a p-type diamond layer to which a p-type dopant is doped at high concent... | 02/04/1997 |
| 5599724 | FET having part of active region formed in semiconductor layer in through hole formed in gate electrode and method for manufacturing the same An N-type source (or drain) region is formed in the surface area of a P-type silicon substrate. A first insulation film is formed on the silicon substrate and a gate electrode is formed on the first insulation film. A second insulation film is formed on t... | 02/04/1997 |
| 5592005 | Punch-through field effect transistor A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inv... | 01/07/1997 |