Class 257/E29.155 - Multiple silicon layers

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E29.154. This
No. of patents: 134
Last issue date: 03/09/2004

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Number	Title	Issue Date
6703672	Polysilicon/amorphous silicon composite gate electrode A polysilicon/amorphous silicon composite layer for improved linewidth control in the patterning of gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The formation of a composite polysilicon/amorphous silicon gate in an integ...	03/09/2004
6693313	Field effect transistors, field effect transistor assemblies, and integrated circuitry The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a...	02/17/2004
6682992	Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into t...	01/27/2004
6670263	Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or mo...	12/30/2003
6653699	Polysilicon/Amorphous silicon gate structures for integrated circuit field effect transistors Gate electrodes for integrated circuit field effect transistors are fabricated by forming a polysilicon layer on a gate insulating layer opposite an integrated circuit substrate, forming an amorphous impurity layer on the polysilicon layer opposite the ga...	11/25/2003
6649518	Method of forming a conductive contact An opening is formed within insulative material to proximate a silicon comprising substrate. Titanium is deposited within the opening to form a first layer comprising titanium suicide. It is exposed to a nitrogen containing plasma effective to transform a...	11/18/2003
6642592	Semiconductor device and method for fabricating same A semiconductor device and method for fabricating the same which improves reliability of the semiconductor device is disclosed. The semiconductor device includes: a first insulating film and a gate electrode sequentially formed on a part of a semiconducto...	11/04/2003
6627951	High speed trench DMOS A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high...	09/30/2003
6620671	Method of fabricating transistor having a single crystalline gate conductor A method of manufacturing an integrated circuit on a substrate provides a gate structure including single crystalline material. The method can provide a first amorphous or polycrystalline semiconductor layer above a top surface of the substrate and patter...	09/16/2003
6620713	Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-fre...	09/16/2003
6607958	Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device, comprising a semiconductor substrate, an insulating film and a gate electrode formed on the semiconductor substrate, source-drain regions formed in the semiconductor substrate, and a metal oxide layer formed selectivel...	08/19/2003
6555867	Flash memory gate coupling using HSG polysilicon A method for improving the gate coupling in a flash memory core includes forming floating gates of memory element stacks by depositing a first polysilicon layer having relatively small grain size on a tunnel oxide layer and then depositing a second polysi...	04/29/2003
6534400	Method for depositing a tungsten silicide layer Disclosed is a method for depositing a tungsten silicide layer on a wafer coated with a polysilicon layer in a CVD process chamber. A surface of the polysilicon layer is pre-treated by introducing a hydrogen compound gas including any elements among group...	03/18/2003
6528362	Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. ...	03/04/2003
6498378	Methods of forming field effect transistors and integrated circuitry The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a...	12/24/2002
6492676	Semiconductor device having gate electrode in which depletion layer can be generated A semiconductor device including a first gate electrode having a first plane provided opposite to a first semiconductor region where a channel is to be formed with a first gate insulation film interposed therebetween; a second gate insulation film includi...	12/10/2002
6486030	Methods of forming field effect transistors and integrated circuitry including TiN gate element The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a...	11/26/2002
6479362	Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof An improved gate electrode provides greater tolerances to higher temperature annealing treatments, and is useful in connection with the formation of self-aligned contacts as are needed for high density embedded DRAM applications. Consistent with one embod...	11/12/2002
6476454	Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device, comprising a semiconductor substrate, an insulating film and a gate electrode formed on the semiconductor substrate, source-drain regions formed in the semiconductor substrate, and a metal oxide layer formed selectivel...	11/05/2002
6468845	Semiconductor apparatus having conductive thin films and manufacturing apparatus therefor In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of ...	10/22/2002
6440829	N-profile engineering at the poly/gate oxide and gate oxide/SI interfaces through NH3 annealing of a layered poly/amorphous-silicon structure A method and structure providing N-profile engineering at the poly/gate oxide and gate oxide/Si interfaces of a layered polysilicon/amorphous silicon structure of a semiconductor device. NH3 annealing provides for the introduction of nitrogen t...	08/27/2002
6432763	Field effect transistor having doped gate with prevention of contamination from the gate during implantation For fabricating a field effect transistor on a semiconductor substrate, a gate dielectric of the field effect transistor is formed on a semiconductor substrate. A doped gate electrode, which may be comprised of silicon germanium (SiGe) for example, is for...	08/13/2002
6413841	MOS type semiconductor device and manufacturing method thereof First, a polysilicon film is formed on a gate oxide film. Next, a polysilicon oxide film is formed on the polysilicon film. Thereafter, the polysilicon film is thermally treated to allow a crystal grain in the polysilicon film to grow from the gate oxide ...	07/02/2002
6380055	Dopant diffusion-retarding barrier region formed within polysilicon gate layer A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separatel...	04/30/2002
6346731	Semiconductor apparatus having conductive thin films In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of ...	02/12/2002
6337264	Simplified method of patterning polysilicon gate in a semiconductor device including an oxime layer as a mask Polysilicon gates are formed with greater accuracy and consistency by depositing an antireflective layer of silicon oxime on the polysilicon layer before patterning. Embodiments also include depositing the polysilicon layer and the silicon oxime layer in ...	01/08/2002
6335297	Method for forming conductive line of semiconductor device Method for forming a conductive line of a semiconductor device which has a high thermal stability and low electrical resistance includes the steps of forming an insulating layer on a semiconductor substrate, sequentially forming a semiconductor layer and ...	01/01/2002
6333229	Method for manufacturing a field effect transitor (FET) having mis-aligned-gate structure A viable T-gate FET is produced even when the cap of the "T" is mis-aligned from the stem of the "T". A subtractive etch is used to selectively etch the material forming the cap of the T-gate and the material forming the stem of the T-gate in order to avo...	12/25/2001
6326664	Transistor with ultra shallow tip and method of fabrication A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode ...	12/04/2001
6306710	Fabrication of a gate structures having a longer length toward the top for formation of a rectangular shaped spacer The gate structure of the MOSFET of the present invention is formed to have a longer length toward the top of the gate structure such that a spacer having a substantially rectangular shaped is formed at the sidewalls of the gate structure. For fabricating...	10/23/2001
6287915	Semiconductor device and manufacturing method therefor In a flash memory that has a floating gate that is formed by a polysilicon layer having grains, a gate electrode is formed on a gate oxide film that is provided on a semiconductor substrate, this gate electrode being formed as a multilayer structure by a ...	09/11/2001
6261705	Poly-si film and a semiconductor device wherein the poly-si film is applied To provide a poly-Si film which has excellence in its characteristics themselves concerning transistor characteristics, such as the diffusion and precipitation of dopant, the interface and surface state or the carrier mobility, and excellence in controlla...	07/17/2001
6221708	Field effect transistor assemblies, integrated circuitry, and methods of forming field effect transistors and integrated circuitry The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a...	04/24/2001
6221744	Method for forming a gate A method for forming a gate on a substrate for manufacturing semiconductor devices is described. The present method comprises the step of providing a gate oxide layer on top of a substrate. A polysilicon layer is overlaid on the gate oxide layer and then,...	04/24/2001
6208004	Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof An improved gate electrode provides greater tolerances to higher temperature annealing treatments, and is useful in connection with the formation of self-aligned contacts as are needed for high density embedded DRAM applications. Consistent with one embod...	03/27/2001
6194296	Method for making planarized polycide Planarized polycide structures and methods for making the same. One embodiment includes a semiconductor structure having an irregular upper surface caused, for example, by the presence of field oxide surrounding an active region of an FET. A layer of poly...	02/27/2001
6180501	Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process This invention relates to the fabrication of integrated circuit devices and more particularly to a method for minimizing the localized mechanical stress problems that can occur when silicided polysilicon gates are used to fabricate narrow channel CMOS dev...	01/30/2001
6171939	Method for forming polysilicon gate electrode A method for forming a polysilicon gate electrode. A semiconductor is provided. A gate oxide layer, a partially doped polysilicon layer and an undoped polysilicon are sequentially formed over the semiconductor substrate. The undoped polysilicon layer, the...	01/09/2001
6165826	Transistor with low resistance tip and method of fabrication in a CMOS process A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first ga...	12/26/2000
6162716	Amorphous silicon gate with mismatched grain-boundary microstructure A method of forming an amorphous-Si (଱-Si) gate with two or more ଱-Si layers with mismatched grains. The first embodiment involves forming two or more amorphous silicon layers over the gate dielectric. The amorphous silicon layers are formed i...	12/19/2000

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Class 257/E29.155 - Multiple silicon layers