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| Number | Title | Issue Date |
| 7391084 | LDMOS transistor device, integrated circuit, and fabrication method thereof An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10), a gate region (1) including a gate semiconductor layer region (2; 2′; 151) on top of a gate insulation layer region (3; 141), source (4... | 06/24/2008 |
| 7323747 | Lateral semiconductor device In a high voltage P-channel MOS transistor formed on a silicon-on-insulator (SOI) substrate, a P+-type source region (8), an N-type body region (4) and an N+-body contact diffusion region (10) are surrounded by a P+ | 01/29/2008 |
| 7306995 | Reduced hydrogen sidewall spacer oxide An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a sp... | 12/11/2007 |
| 7265015 | Use of chlorine to fabricate trench dielectric in integrated circuits Chlorine is incorporated into pad oxide (110) formed on a silicon substrate (120) before the etch of substrate isolation trenches (134). The chlorine enhances the rounding of the top corners (140C) of the trenches when a silicon oxide lin... | 09/04/2007 |
| 7045852 | Floating gate memory cells with increased coupling radio A method to improve the coupling ratio between a control gate (18) and a floating gate (14) of a floating gate non-volatile semiconductor device is described. In a stacked gate floating gate transistor according to the invention, a conductive spacer ( | 05/16/2006 |
| 6927435 | Semiconductor device and its production process A semiconductor device comprising a semiconductor substrate, gate insulators formed on the substrate, and gate electrodes formed on the gate insulators, the gate insulators which are mainly composed of a material selected from titanium oxide, zirconium oxide and haf... | 08/09/2005 |
| 6841826 | Low-GIDL MOSFET structure and method for fabrication A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing... | 01/11/2005 |
| 6700167 | Semiconductor device having thick insulating layer under gate side walls A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the ga... | 03/02/2004 |
| 6696725 | Dual-gate MOSFET with channel potential engineering A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions... | 02/24/2004 |
| 6693335 | Semiconductor raised source-drain structure A semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the d... | 02/17/2004 |
| 6686636 | Semiconductor raised source-drain structure A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication wi... | 02/03/2004 |
| 6683355 | Semiconductor raised source-drain structure A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication wi... | 01/27/2004 |
| 6680233 | Semiconductor device formed with disposable spacer and liner using high-K material and method of fabrication A semiconductor device and method of manufacture. A liner composed of a high-K material having a relative permittivity of greater than 10 is formed adjacent at least the sidewalls of a gate. Sidewall spacers are formed adjacent the gate and spaced apart f... | 01/20/2004 |
| 6680224 | Methods of forming and operating field effect transistors having gate and sub-gate electrodes Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the chan... | 01/20/2004 |
| 6677651 | Semiconductor device and method for manufacturing the same A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the ga... | 01/13/2004 |
| 6677642 | Field effect transistor structure and method of manufacture A field effect transistor structure is formed with a body semiconductor layer (5) having source (9), body (7), drift region and drain (11). An upper semiconductor layer (21) is separated from the body by an oxide layer (17). The upper semiconductor layer ... | 01/13/2004 |
| 6674130 | High performance PD SOI tunneling-biased MOSFET A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made s... | 01/06/2004 |
| 6674139 | Inverse T-gate structure using damascene processing A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the ce... | 01/06/2004 |
| 6670667 | Asymmetric gates for high density DRAM A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment... | 12/30/2003 |
| 6664153 | Method to fabricate a single gate with dual work-functions A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-f... | 12/16/2003 |
| 6664156 | Method for forming L-shaped spacers with precise width control A method of fabrication of L-shaped spacers in a semiconductor device. A gate structure is provided over a substrate. We form a first dielectric layer over the gate dielectric layer and the substrate. Next, a second dielectric layer is formed over the fir... | 12/16/2003 |
| 6661055 | Transistor in semiconductor devices The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which a voltage is applied apart from a gate electrode and forme... | 12/09/2003 |
| 6652989 | Structure and method for controlling band offset and alignment at a crystalline oxide-on-semiconductor interface A crystalline oxide-on-semiconductor structure and a process for constructing the structure involves a substrate of silicon, germanium or a silicon-germanium alloy and an epitaxial thin film overlying the surface of the substrate wherein the thin film con... | 11/25/2003 |
| 6639288 | Semiconductor device with a particular conductor arrangement A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high a... | 10/28/2003 |
| 6639264 | Method and structure for surface state passivation to improve yield and reliability of integrated circuit structures A method for passivating surface states in an integrated circuit structure having a gate conductor with a gate dielectric layer. The method comprises the step of fabricating a solid state source of fluorine in close proximity to the gate dielectric layer.... | 10/28/2003 |
| 6635938 | Semiconductor device and manufacturing method thereof A polysilicon nitride film is formed to cover a polysilicon gate. By heat treatment of the silicon nitride film in an oxygen atmosphere, a silicon oxinitride film is formed. By anisotropically etching the silicon oxinitride film and the silicon nitride fi... | 10/21/2003 |
| 6633070 | Semiconductor device A field-effect transistor including a gate electrode, silicon layers, and source and drain regions at a surface of a silicon substrate. Sidewall insulating films on the opposite side surfaces of the gate electrode are located between the gate electrode an... | 10/14/2003 |
| 6630712 | Transistor with dynamic source/drain extensions A method of fabricating an integrated circuit with a transistor having less susceptibility to off-state leakage current and short-channel effect is disclosed. The transistor includes high-K gate dielectric spacers and a T-shaped gate conductor. The high-K... | 10/07/2003 |
| 6627536 | Semiconductor blocking layer for preventing UV radiation damage to MOS gate oxides A system and apparatus is provided for preventing damage to gate oxide due to ultraviolet radiation associated with semiconductor processes. Included is a substrate and a gate formed on the substrate. The gate includes a gate material layer and a gate oxi... | 09/30/2003 |
| 6624093 | Method of producing high dielectric insulator for integrated circuit A high dielectric insulator for integrated circuit use is produced by depositing hafnium on a silicon dioxide surface of a silicon wafer and then promoting a solid-state reaction between the silicon dioxide and the hafnium by heating the wafer to produce ... | 09/23/2003 |
| 6620703 | Method of forming an integrated circuit using an isolation trench having a cavity formed by reflowing a doped glass mask layer Isolation characteristics of an isolation trench can be enhanced. Elements to be isolated by an isolation trench (STI 2) are formed in active semiconductor regions shown by arrows 30 and 31 on a semiconductor substrate 1. The STI 2 is filled with SiOF.... | 09/16/2003 |
| 6602720 | Single transistor ferroelectric transistor structure with high-K insulator and method of fabricating same A ferroelectric transistor gate structure with a ferroelectric gate and a high-k insulator is provided. The high-k insulator may serve as both a gate dielectric and an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroel... | 08/05/2003 |
| 6597045 | Semiconductor raised source-drain structure A semiconductor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication w... | 07/22/2003 |
| 6596606 | Semiconductor raised source-drain structure A method of forming a semiconductor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping laye... | 07/22/2003 |
| 6593618 | MIS semiconductor device having an elevated source/drain structure In the first aspect of the invention, a semiconductor device can effectively suppress the adverse short channel effect and the possible occurrence of junction leak current and has a low resistance diffusion layer to realize a short propagation delay time ... | 07/15/2003 |
| 6593198 | Semiconductor device and method for fabricating the same Gate insulating film, gate electrode made up of lower and upper gate electrodes, and on-gate passivation film are formed in this order on an Si substrate. Then, a sidewall is formed as a stack of an oxynitride sidewall having an L-shaped cross section and... | 07/15/2003 |
| 6579770 | Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled po... | 06/17/2003 |
| 6548362 | Method of forming MOSFET with buried contact and air-gap gate structure A method of forming MOSFET with buried contacts and air-gap gate structure is disclosed. The method comprises following steps firstly, a gate is formed of pad oxide layer and a nitride layer sequentially on a silicon substrate, which has trench isolations... | 04/15/2003 |
| 6541362 | Methods of forming semiconductor structures One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least... | 04/01/2003 |
| 6528399 | MOSFET transistor with short channel effect compensated by the gate material A MOSFET transistor comprising a gate made of silicon-germanium alloy, formed on a single crystal silicon substrate by means of a thin insulating layer, and drain and source regions implanted in the substrate on each side of the gate, characterized in tha... | 03/04/2003 |
