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| Number | Title | Issue Date |
| 6703279 | Semiconductor device having contact of Si-Ge combined with cobalt silicide The present invention provides a metal contact of SiGe combined with cobalt silicide and cobalt. The contact resistance is greatly lowered due to both the low Schottky Barrier Height of SiGe and the low sheet resistance of cobalt silicide. The cobalt laye... | 03/09/2004 |
| 6703296 | Method for forming metal salicide A method for forming a metal salicide layer on a shallow junction is described. A substrate having a gate structure thereon and a shallow junction therein is provided. An atomic layer deposition (ALD) process is then performed to deposit a tungsten salici... | 03/09/2004 |
| 6693001 | Process for producing semiconductor integrated circuit device A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity C... | 02/17/2004 |
| 6688584 | Compound structure for reduced contact resistance Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first r... | 02/10/2004 |
| 6690061 | MOS Semiconductor device The semiconductor device according to an aspect of the present invention includes: a semiconductor substrate of a first conductive type; a first semiconductor layer of the first conductive type formed on the main surface of the semiconductor substrate, th... | 02/10/2004 |
| 6677646 | Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fab... | 01/13/2004 |
| 6674099 | MISFET A metal insulator semiconductor field effect transistor (MISFET) is disclosed comprising a source layer being made with a material having a source band-gap (EG2) and a source mid-gap value (EGM2), the source layer having a source Fermi-Level (EF2). A drai... | 01/06/2004 |
| 6667202 | Semiconductor device and method for making the same A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the su... | 12/23/2003 |
| 6657301 | Contact structure, method of forming the same, semiconductor device, and method of manufacturing the same A ternary metal silicide layer is formed between a silicon substrate and a barrier layer, in a contact structure including: a substrate having a silicon part; an insulating layer formed on the substrate, and having a connection hole that reaches the silic... | 12/02/2003 |
| 6657265 | Semiconductor device and its manufacturing method A semiconductor device includes metal silicide films formed on the surface of a source-drain region and of a gate electrode. On the metal silicide films, impurity regions are formed of a conductivity type opposite to the conductivity type of the source-dr... | 12/02/2003 |
| 6645861 | Self-aligned silicide process for silicon sidewall source and drain contacts A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region... | 11/11/2003 |
| 6639319 | Conductive structure in an integrated circuit A method of forming a local interconnect structure is provided. A first barrier layer comprising sputtered titanium nitride is formed over a topographical structure situated upon a field oxide region within a semiconductor substrate. A hard mask layer com... | 10/28/2003 |
| 6635535 | Dense trench MOSFET with decreased etch sensitivity to deposition and etch processing A power MOSFET 100 has a source metal 112 that contacts silicided source regions 114 through vias 160 etched in an insulating layer 200. The silicide layer 225 provides for a relatively small but highly conductive contact and thus reduces RDSON. The insul... | 10/21/2003 |
| 6633071 | Contact on a P-type region The present invention relates to a contacting structure on a lightly-doped P-type region of a semiconductor component, this P-type region being positively biased during the on-state operation of said component, including, on the P region a layer of a plat... | 10/14/2003 |
| 6627951 | High speed trench DMOS A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high... | 09/30/2003 |
| 6621145 | Semiconductor device having a metal-semiconductor junction with a reduced contact resistance A metal-semiconductor junction comprises a wiring metal layer and a semiconductor layer. To reduce the contact resistance of the junction, a region doped with an n- or p-type impurity and having a high carrier concentration of 1021 cm-3 | 09/16/2003 |
| 6586345 | Method of manufacturing a semiconductor device wiring layer having an oxide layer between the polysilicon and silicide layers In forming a conduction film in a semiconductor device, after an uneven natural oxide film on a silicon film has been once removed, an even and clean silicon oxide film is formed by an oxidizing chemical solution treatment. After that, a silicide film is ... | 07/01/2003 |
| 6583510 | Semiconductor device with varying thickness gold electrode An electrode for a semiconductor device includes a gold-containing thin film and a gold-containing plated film on the thin film. The plated film covers the entire thin film. No open surface is present between the thin gold film and the gold plating so no ... | 06/24/2003 |
| 6566209 | Method to form shallow junction transistors while eliminating shorts due to junction spiking A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first ele... | 05/20/2003 |
| 6562699 | Process for manufacturing semiconductor device By removing halogen atoms existing on the surface of the silicon layer and in the subsurface thereof so that the concentration of halogen atoms becomes 100 ppm or lower and forming an electrode on the resulting silicon layer, the electrode which has a low... | 05/13/2003 |
| 6559041 | Semiconductor device and method for manufacturing same In a semiconductor device that uses a low-resistance ohmic contact and which is suitable for high-speed operation, the ohmic contacts are formed by a single-crystal CoSi2 film that is formed on the (100) surface of a silicon substrate.... | 05/06/2003 |
| 6534871 | Device including an epitaxial nickel silicide on (100) Si or stable nickel silicide on amorphous Si and a method of fabricating the same An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a... | 03/18/2003 |
| 6531750 | Shallow junction transistors which eliminating shorts due to junction spiking A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first ele... | 03/11/2003 |
| 6522002 | Semiconductor device and method of manufacturing the same In a semiconductor device, a CoSi2 film is interposed between a pluglike contact and a barrier metal film as a silicide film. Consequently, excess reaction can be suppressed on a Ti/polysilicon interface between the pluglike contact or a plugli... | 02/18/2003 |
| 6521956 | Semiconductor device having contact of Si-Ge combined with cobalt silicide The present invention provides a metal contact of SiGe combined with cobalt silicide and cobalt. The contact resistance is greatly lowered due to both the low Schottky Barrier Height of SiGe and the low sheet resistance of cobalt silicide. The cobalt laye... | 02/18/2003 |
| 6492264 | Semiconductor device having a silicide layer with silicon-rich region and method for making the same A semiconductor device includes a substrate; a semiconductor region formed on the substrate; and a silicide layer as a contact layer formed directly contacting the semiconductor region; wherein the silicide layer is made to be rich in silicon while includ... | 12/10/2002 |
| 6486048 | Method for fabricating a semiconductor device using conductive oxide and metal layer to silicide source + drain A method for fabricating semiconductor device capable of forming silicide suitable for highly integrated semiconductor device comprising the steps of: forming a conductive oxide layer and metal layer on a substrate having a gate and source/drain regions; ... | 11/26/2002 |
| 6452244 | Film-like composite structure and method of manufacture thereof On a semiconductor layer 1 consisting of a substrate of a semiconductor single crystal or the like, a metallic layer 2 of a thickness of 20 nm or less is formed. The metallic layer 2 comprises a first area A directly contacting with the semiconductor laye... | 09/17/2002 |
| 6433387 | Lateral bipolar transistor Lateral bipolar transistor, in which a thin diffusion barrier (4) is applied to a base region (10) between an emitter region (9) and a collector region (11), and there is present, on said barrier, a base electrode (8) which is provided for low-resistance ... | 08/13/2002 |
| 6410984 | Conductive structure in an integrated circuit A method of forming a local interconnect structure is provided. A first barrier layer comprising sputtered titanium nitride is formed over a topographical structure situated upon a field oxide region within a semiconductor substrate. A hard mask layer com... | 06/25/2002 |
| 6348735 | Electrode for semiconductor device and method for manufacturing same The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interla... | 02/19/2002 |
| 6342421 | Semiconductor device and manufacturing method thereof A method of manufacturing a semiconductor device including the steps of forming an insulating film on a silicon region of a substrate having the silicon region on a surface the insulating film having an opening for forming an exposed region of the silicon... | 01/29/2002 |
| 6331466 | Insulated gate semiconductor device and manufacturing method thereof An insulated gate semiconductor device in which the ON voltage is decreased by providing strip like trenches (207) having gate electrodes (210) buried therein are formed in an upper main surface of a semiconductor base body (200), and an N+ emi... | 12/18/2001 |
| 6331356 | Patterns of electrically conducting polymers and their application as electrodes or electrical contacts Electronic devices having patterned electrically conductive polymers providing electrical connection thereto and methods of fabrication thereof are described. Liquid crystal display cells are described having at least one of the electrodes providing a bia... | 12/18/2001 |
| 6323525 | MISFET semiconductor device having relative impurity concentration levels between layers A semiconductor device having a MISFET with an EV source/drain structure has a gate electrode formed on part of a first p-type semiconductor layer via a gate insulating film. A second n+ -type semiconductor layer is formed in the prospective so... | 11/27/2001 |
| 6323508 | Insulated gate semiconductor device and manufacturing method thereof An insulated gate semiconductor device in which the ON voltage is decreased by providing strip like trenches (207) having gate electrodes (210) buried therein are formed in an upper main surface of a semiconductor base body (200), and an N+ emi... | 11/27/2001 |
| 6297109 | Method to form shallow junction transistors while eliminating shorts due to junction spiking A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first ele... | 10/02/2001 |
| 6292390 | Semiconductor device A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE | 09/18/2001 |
| 6288430 | Semiconductor device having silicide layer with siliconrich region and method for making the same A semiconductor device includes a substrate; a semiconductor region formed on the substrate; and a silicide layer as a contact layer formed directly contacting the semiconductor region; wherein the silicide layer is made to be rich in silicon while includ... | 09/11/2001 |
| 6278163 | HV transistor structure and corresponding manufacturing method An HV transistor integrated in a semiconductor substrate with a first type of conductivity, comprising a gate region included between corresponding drain and source regions, and being of the type wherein at least said drain region is lightly doped with a ... | 08/21/2001 |
