Class 257/E29.136 - Characterized by surface lay-out (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E29.134. This
No. of patents: 175
Last issue date: 07/22/2008

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Number	Title	Issue Date
7402874	One time programmable EPROM fabrication in STI CMOS technology The formation of a one time programmable (OTP) transistor based electrically programmable read only memory (EPROM) cell (100) is disclosed. The cell (100) includes multiple concentric rings (108, 110) out of which gate structures are formed. An ...	07/22/2008
7394120	Semiconductor device having a shaped gate electrode and method of manufacturing the same An MIS transistor includes a gate electrode located to intersect a device region of a semiconductor substrate isolated by a device isolation region, and source and drain regions formed in the semiconductor substrate at both sides of the gate electrode region and ele...	07/01/2008
7282772	Low-capacitance contact for long gate-length devices with small contacted pitch Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sectio...	10/16/2007
6703895	Semiconductor component and method of operating same An embodiment of a method of redistributing power in a semiconductor component includes varying a saturation current between a drain terminal (330) and a source terminal (320) of a field effect transistor (FET) (200, 500). The FET is at least a portion of...	03/09/2004
6703664	Power FET device A power FET device includes a semiconductor wafer substrate having first and second surfaces, a gate electrode extending over the first surface of the substrate but insulated therefrom, and a drain electrode extending over the second surface of the substr...	03/09/2004
6700158	Trench corner protection for trench MOSFET A method of making a trench MOSFET structure having upper trench corner protection, the method not requiring trench corner rounding or sacrificial oxide/strip steps. The trench MOSFET structure fabricated according to the method of the present invention e...	03/02/2004
6696323	Method of manufacturing semiconductor device having trench filled up with gate electrode In a semiconductor device, a p-type base region is provided in an n- -type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+ -type source region extends in the ...	02/24/2004
6693011	Power MOS element and method for producing the same A power MOS element includes a drift region with a doping of a first doping type, a channel region with a doping of a second doping type which is complementary to said first doping type and which borders on said channel region and said drift region, and a...	02/17/2004
6683352	Semiconductor device structure A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is dispose...	01/27/2004
6677210	High voltage transistors with graded extension High voltage transistors with high breakdown voltages are provided. These high voltage transistors are formed with graded drain extension regions. The concentration of charge carriers increases farther away from the gate across each drain extension region...	01/13/2004
6674108	Gate length control for semiconductor chip design A semiconductor device includes first and second polysilicon areas on a chip. The first polysilicon area corresponds to circuit elements of the semiconductor device. At least some of the first polysilicon corresponds to polysilicon gates. At least some of...	01/06/2004
6674130	High performance PD SOI tunneling-biased MOSFET A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made s...	01/06/2004
6653695	Semiconductor device with an improved gate electrode pattern Disclosed is a semiconductor device using a gate electrode such as an SRAM, wherein the electrode pattern is a formed with fidelity to a reticle pattern through no complicated layout design. The gate electrode pattern is formed in an area smaller than tha...	11/25/2003
6653740	Vertical conduction flip-chip device with bump contacts on single surface A flip-chip MOSFET structure has a vertical conduction semiconductor die in which the lower layer of the die is connected to a drain electrode on the top of the die by a diffusion sinker or conductive electrode. The source and gate electrodes are also for...	11/25/2003
6653691	Radio frequency (RF) power devices having faraday shield layers therein Integrated power devices include a plurality of field effect transistor unit cells and a Faraday shield layer that reduces parasitic gate-to-drain capacitance (Cgd) and concomitantly improves high frequency switching performance. These power devices may i...	11/25/2003
6649985	Insulated-gate semiconductor device for a rectifier An insulated-gate semiconductor device comprises a source region (S) formed on a predetermined semiconductor substrate such as a ball semiconductor, a drain region (D) formed on the semiconductor substrate at a distance from the source region; and a gate ...	11/18/2003
6649975	Vertical power devices having trench-based electrodes therein Vertical power devices include a semiconductor substrate having a drift region of first conductivity type therein and first and second stripe-shaped trenches that extend in the semiconductor substrate and define a drift region mesa therebetween. First and...	11/18/2003
6642600	Insulated gate semiconductor device having first trench and second trench connected to the same A second trench (105b) is formed inside a semiconductor layer (102), penetrating a base layer (103) and moreover extends along a second direction (D2) while being connected to one end portion of each first portion (P1) of a first trench (105a) extending a...	11/04/2003
6639275	Semiconductor device with vertical MOSFET A semiconductor device improves the gate withstand voltage of vertical MOSFETs and raises their operation speed. The gate electrode is formed in the trench of the second semiconductor layer. The interlayer dielectric layer has the contact hole that expose...	10/28/2003
6627499	Semiconductor device and method of manufacturing the same Formed in a part of the base region is an impurity diffusion region extending in a vertical direction and having an impurity concentration lower than that in the other portion of the base region. By the formation of the impurity diffusion region, the depl...	09/30/2003
6627950	Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using sp...	09/30/2003
6613623	High fMAX deep submicron MOSFET A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A f...	09/02/2003
6586807	Semiconductor integrated circuit device A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end thereof to the other end thereof. The gate electrode has a g...	07/01/2003
6566185	Method of manufacturing a plural unit high frequency transistor A semiconductor device has a plurality of transistor units each of which is constituted by a unit prepared by arranging a plurality of unit cells each made up of a drain, gate, and source adjacent to each other on the major surface of a semiconductor subs...	05/20/2003
6555877	NMOSFET with negative voltage capability formed in P-type substrate and method of making the same A semiconductor device (10,50) is disclosed which can accommodate a negative voltage on its source using a P-type substrate (12) which is connected to ground potential. A first embodiment illustrates a device which can handle high voltage applications as ...	04/29/2003
6555883	Lateral power MOSFET for high switching speeds A lateral power metal-oxide-semiconductor field effect transistor (MOSFET) having a gate structure in which the insulated gate is coupled to the gate electrode through contacts at a plurality of locations. The source electrode includes first and second se...	04/29/2003
6541827	Semiconductor device having a patterned insulated gate An n-type semiconductor layer, for example, is provided to be a drain region (1). A plurality of p-type diffusion regions (body regions) are formed regularly on the surface of the semiconductor layer. And an n-type diffusion region is formed, as a source ...	04/01/2003
6534823	Semiconductor device A semiconductor body has source and drain regions (4 and 5; 4' and 5') spaced apart by a body region (6; 6') and a drain drift region (50; 50') and both meeting the same surface (3a) of the semiconductor body. An insulated gate structure (7; 70'; 700) is ...	03/18/2003
6525360	Semiconductor device using a shallow trench isolation In a MOS transistor using shallow trench isolation, a pattern of an element formation region has a shape of a modified hexagon in which a hexagon is compressed into a shape like a rhombus in a direction perpendicular to an extension direction of a gate el...	02/25/2003
6518105	High performance PD SOI tunneling-biased MOSFET A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made s...	02/11/2003
6501155	Semiconductor apparatus and process for manufacturing the same To provide a semiconductor apparatus that secures high ESD protection capability and yet reduces leak current. Cut sections 64-1 and 64-2 are provided in end sections of a second edge 62 of a drain region 22. When a distance between a first edge 60 of a source...	12/31/2002
6501136	High-speed MOSFET structure for ESD protection A multi-gate-finger MOSFET structure positions the gate element over a channel between drain and source diffusion regions, such that the entire structure is within the active region in a substrate. The gate/channel-to-drain and gate/channel-to-source diff...	12/31/2002
6472708	Trench MOSFET with structure having low gate charge A trench MOSFET includes a plurality of trench segments in an upper surface of an epitaxial layer, extending through a second conductivity type region into a first conductivity type epitaxial region, each segment at least partially separated from an adjac...	10/29/2002
6462389	Semiconductor device The present invention provides a semiconductor device that has reduced a short-channel effect by preventing the effective channel length at the sides of a channel of a transistor from decreasing by forming the length of a gate electrode to be different ac...	10/08/2002
6445052	Power lateral diffused MOS transistor The present invention provides a power lateral diffused metal-oxide semiconductor (power LD MOS) transistor positioned in an active area of a substrate on a semiconductor wafer. The power LD MOS transistor has a source/drain, a first metal layer and a hex...	09/03/2002
6436773	Fabrication of test field effect transistor structure For fabricating a test field effect transistor on a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate, and a layer of gate electrode material is deposited on the layer of gate dielectric material. A d...	08/20/2002
6420747	MOSCAP design for improved reliability Reliable metal oxide semiconductor (MOS) devices which exhibit little or no oxide breakdown at the Rx edge during device biasing are provided. The improved reliability is obtained by forming a contact to the polysilicon top conductor over a sub...	07/16/2002
6404022	AM/PM non-linearities in FETs When a field effect transistor (e.g., an LDMOSFET) saturates, the electrons traveling through the device slow down. This causes a phase shift with respect to electrons that travel through the device when the device is not saturated. By providing a shorter...	06/11/2002
6392279	Semiconductor device having LDD structure adapted to lower parasitic capacitance and parasitic resistance The MOS transistor incorporated in a semiconductor device comprises a gate electrode formed on a semiconductor substrate through the medium of a gate insulating film, a first impurity introduced area of an LDD structure composed of a low-concentration imp...	05/21/2002
6391725	Semiconductor device and method for fabricating the same A semiconductor device which is applied to access transistors of an SRAM cell to improve its operation performance and a method for fabricating the same are disclosed. The semiconductor device includes a gate insulating layer formed on a semiconductor sub...	05/21/2002

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Class 257/E29.136 - Characterized by surface lay-out (EPO)