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| Number | Title | Issue Date |
| 7432563 | Method for producing a semiconductor component and semiconductor component produced by the same A method for producing a gate head which can be precisely scaled and for reducing parasitic capacities, for a semiconductor component comprising an at least approximately T-shaped electrode. ... | 10/07/2008 |
| 7368769 | MOS transistor having a recessed gate electrode and fabrication method thereof A metal oxide semiconductor (MOS) transistor having a recessed gate electrode and a fabrication method thereof are provided. The MOS transistor includes a semiconductor substrate and an isolation layer formed in a predetermined region of the semiconductor substrate ... | 05/06/2008 |
| 7339241 | FinFET structure with contacts A FinFET, which by its nature has both elevated source/drains and an elevated channel that are portions of an elevated semiconductor portion that has parallel fins and one source/drain on one side of the fins and another source/drain on the other side of the fins, h... | 03/04/2008 |
| 7326621 | Method of fabricating a recess channel array transistor using a mask layer with a high etch selectivity with respect to a silicon substrate A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After formin... | 02/05/2008 |
| 7323746 | Recess gate-type semiconductor device and method of manufacturing the same A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess t... | 01/29/2008 |
| 7176534 | Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch The present invention provides a method for fabricating low-resistance, sub-0.1 μm channel T-gate MOSFETs that do not exhibit any poly depletion problems. The inventive method employs a damascene-gate processing step and a chemical oxide removal etch to fabricate s... | 02/13/2007 |
| 7109549 | Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device having a plurality of memory cells arranged in a first direction and a second direction perpendicular to the first direction, each memory cell comprising a first insulating film formed on a semiconductor substrate, a floating gate... | 09/19/2006 |
| 6927435 | Semiconductor device and its production process A semiconductor device comprising a semiconductor substrate, gate insulators formed on the substrate, and gate electrodes formed on the gate insulators, the gate insulators which are mainly composed of a material selected from titanium oxide, zirconium oxide and haf... | 08/09/2005 |
| 6699755 | Method for producing a gate A method for producing a gate on a semiconductor substrate. The semiconductor substratehas a first oxide layer, a conductive layer, a silicide layer, and a hard mask formed thereon. The method includes defining the hard mask to form a pattern of the gate,... | 03/02/2004 |
| 6686613 | Punch through type power device A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is ... | 02/03/2004 |
| 6661066 | Semiconductor device including inversely tapered gate electrode and manufacturing method thereof A semiconductor device and manufacturing method including a MOSFET having a trench-type element isolation structure (2) formed on a main surface of a semiconductor substrate (1). A pair of extensions (3) and source/drain regions (4) are selectively formed... | 12/09/2003 |
| 6656824 | Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch The present invention provides a method for fabricating low-resistance, sub-0.1 μm channel T-gate MOSFETs that do not exhibit any poly depletion problems. The inventive method employs a damascene-gate processing step and a chemical oxide removal etch to ... | 12/02/2003 |
| 6656808 | Transistor having variable width gate electrode and method of manufacturing the same A transistor includes a substrate and a gate electrode formed on the substrate and having a wider upper portion than lower portion. A spacer is formed on the side wall of the gate electrode from the upper portion to the lower portion of the gate electrode... | 12/02/2003 |
| 6649462 | Semiconductor device and method of manufacturing the same including T-shaped gate A gate insulating film is provided on a channel region. A gate electrode includes a lower part and an upper part. The lower part has a lower surface and sides, and the upper part has a lower surface. The lower surface of the lower part contacts the gate i... | 11/18/2003 |
| 6649974 | Field-effect controlled semiconductor device having a non-overlapping gate electrode and drift region and its manufacturing method A semiconductor component includes a first connection zone of a first conductivity type for providing a contact at a first side of a semiconductor body and a second connection zone of the first conductivity type for providing a contact at the second side ... | 11/18/2003 |
| 6649460 | Fabricating a substantially self-aligned MOSFET The present invention includes methods and structures for forming at least a substantially self-aligned MOSFET. According to the present invention, a method of fabricating a semiconductor device includes providing a substrate; providing first materials (s... | 11/18/2003 |
| 6649979 | Method of manufacturing MOSFET and structure thereof A method of manufacturing an MOSFET. A substrate is provided. A trench filled with an insulating layer is formed in the substrate. The upper portion of the insulating layer is removed and then a spacer is formed on the side-wall of the trench. A sacrifici... | 11/18/2003 |
| 6646326 | Method and system for providing source/drain-gate spatial overlap engineering for low-power devices A method and system for providing a semiconductor device on a substrate are disclosed. The method and system include providing a tunneling barrier on the substrate and providing at least one gate on the tunneling barrier. The at least one of gate includes... | 11/11/2003 |
| 6645821 | Method of producing a thin film resistor in an integrated circuit A thin film resistor (60) is contained between two metal interconnect layers (40, 100) of an integrated circuit. Contact may be made to the resistor (60) through vias (95) from the metal layer (100) above the resistor (60) to both the thin film resistor (... | 11/11/2003 |
| 6645840 | Multi-layered polysilicon process A method for forming a notched MOS gate structure is described. A multi-layer gate structure is formed (150) where the top layer (140) oxidizes at a faster rate compared to the bottom layer (130). This results in the formation of a notch (165) in the gate... | 11/11/2003 |
| 6638801 | Semiconductor device and its manufacturing method A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than... | 10/28/2003 |
| 6632731 | Structure and method of making a sub-micron MOS transistor A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second sel... | 10/14/2003 |
| 6633070 | Semiconductor device A field-effect transistor including a gate electrode, silicon layers, and source and drain regions at a surface of a silicon substrate. Sidewall insulating films on the opposite side surfaces of the gate electrode are located between the gate electrode an... | 10/14/2003 |
| 6630712 | Transistor with dynamic source/drain extensions A method of fabricating an integrated circuit with a transistor having less susceptibility to off-state leakage current and short-channel effect is disclosed. The transistor includes high-K gate dielectric spacers and a T-shaped gate conductor. The high-K... | 10/07/2003 |
| 6627558 | Apparatus and method for selectively restricting process fluid flow in semiconductor processing A semiconductor processing apparatus (10) is disclosed which includes a process chamber (12) and at least one substrate support (18) disposed within the process chamber (12) operable to support a substrate wafer (20). The semiconductor processing apparatu... | 09/30/2003 |
| 6624057 | Method for making an access transistor Methods are disclosed for the fabrication of novel polysilicon structures having increased surface areas to achieve lower resistances after silicidation. The structures are applicable, for example, to semiconductor interconnects, polysilicon gate, and cap... | 09/23/2003 |
| 6624486 | Method for low topography semiconductor device formation A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a p... | 09/23/2003 |
| 6624483 | Semiconductor device having an insulated gate and a fabrication process thereof A semiconductor device includes a T-shaped gate on a gate insulation film, wherein the T-shaped gate includes a lower polycrystal layer containing Si and Ge and an upper polycrystal layer of polysilicon.... | 09/23/2003 |
| 6620703 | Method of forming an integrated circuit using an isolation trench having a cavity formed by reflowing a doped glass mask layer Isolation characteristics of an isolation trench can be enhanced. Elements to be isolated by an isolation trench (STI 2) are formed in active semiconductor regions shown by arrows 30 and 31 on a semiconductor substrate 1. The STI 2 is filled with SiOF.... | 09/16/2003 |
| 6620653 | Semiconductor device and method of manufacturing the same A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is ... | 09/16/2003 |
| 6613623 | High fMAX deep submicron MOSFET A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A f... | 09/02/2003 |
| 6615391 | Current controlled multi-state parallel test for semiconductor device A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS a... | 09/02/2003 |
| 6593450 | 2,7-aryl-9-substituted fluorenes and 9-substituted fluorene oligomers and polymers The invention relates to 2,7-substituted-9-substituted fluorenes and 9-substituted fluorene oligomers and polymers. The fluorenes, oligomers and polymers are substituted at the 9-position with two hydrocarbyl moieties which may optionally contain one or m... | 07/15/2003 |
| 6589830 | Self-aligned process for fabricating power MOSFET with spacer-shaped terraced gate A process forms a power semiconductor device with reduced input capacitance and improved switching speed. A substrate with an epitaxial has an oxide layer patterned to form a narrow terraced gate. A gate oxide layer is formed on the upper surface of the e... | 07/08/2003 |
| 6566211 | Surface modified interconnects An interconnect structure having refractory sidewalls 240 for enhanced yield, performance and reliability. The primary purpose of the refractory metal 240 is to getter sidewall impurities, residual polymers, and corrosive species by-products from the plas... | 05/20/2003 |
| 6566216 | Method of manufacturing a trench transistor To provide a semiconductor device and a process for manufacturing the same which is capable of suppressing short channel effect and preventing a current from leaking between a contact and a silicon substrate. The semiconductor device of the present invent... | 05/20/2003 |
| 6562687 | MIS transistor and method for making same on a semiconductor substrate The invention relates to an MIS transistor comprising a channel region (118), source (114) and drain (116) regions arranged on either side of the channel, and a gate (150) set closely above the channel region. According to the invention, the channel has a... | 05/13/2003 |
| 6555425 | Method for manufacturing transistor A method of manufacturing a transistor. The method comprising the steps of providing a substrate. The substrate comprises a gate oxide layer formed thereon, a polysilicon layer formed on the gate oxide layer, an offset spacer formed on a sidewall of the p... | 04/29/2003 |
| 6551883 | MOS device with dual gate insulators and method of forming the same A MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insu... | 04/22/2003 |
| 6544873 | Methods of fabricating integrated circuit field effect transistors including multilayer gate electrodes having narrow and wide conductive layers An integrated circuit field effect transistor includes a multilayer gate electrode having a first conductive layer and a second conductive layer on the first conductive layer, wherein the second conductive layer is wider than the first conductive layer. T... | 04/08/2003 |
