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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 7220634 | NROM memory cell, memory array, related devices and methods An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing... | 05/22/2007 |
| 6841826 | Low-GIDL MOSFET structure and method for fabrication A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing... | 01/11/2005 |
| 6700156 | Insulated gate semiconductor device An insulated gate semiconductor device includes a first semiconductor layer of a first conductivity type. A plurality of second semiconductor layers of a second conductivity type selectively formed in a surface area of the first semiconductor layer. At le... | 03/02/2004 |
| 6696726 | Vertical MOSFET with ultra-low resistance and low gate charge A vertical trench double-diffused metal-oxide-semiconductor (DMOS) field effect transistor characterized by a reduced drain-to-source resistance and a lower gate charge and providing a high transconductance and an enhanced frequency response.... | 02/24/2004 |
| 6690070 | Insulated gate semiconductor device and its manufacturing method A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. ... | 02/10/2004 |
| 6673681 | Process for forming MOS-gated power device having segmented trench and extended doping zone A process for constructing a trench MOS-gated device includes: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the t... | 01/06/2004 |
| 6674124 | Trench MOSFET having low gate charge A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier ... | 01/06/2004 |
| 6674139 | Inverse T-gate structure using damascene processing A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the ce... | 01/06/2004 |
| 6670685 | Method of manufacturing and structure of semiconductor device with floating ring structure A high voltage semiconductor device includes a drain region disposed within a semiconductor substrate. The semiconductor device further includes a field oxide layer disposed outwardly from the drain region of the semiconductor substrate. The semiconductor... | 12/30/2003 |
| 6667213 | Method of fabricating a high-voltage transistor with a multi-layered extended drain structure A method for fabricating a high-voltage transistor with an extended drain region includes forming parallel arranged drift regions, each of which is interleaved with an insulating layer and a conducting layer that functions as a field plate. Source and bod... | 12/23/2003 |
| 6664594 | Power MOS device with asymmetrical channel structure for enhanced linear operation capability A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the devi... | 12/16/2003 |
| 6660603 | Higher voltage drain extended MOS transistors with self-aligned channel and drain extensions An integrated circuit drain extension transistor. A transistor gate (72) is formed over a CMOS n-well region (10). A transistor source extension region (50), and drain extension region (52) are formed in the CMOS well region (10). A transistor region (90)... | 12/09/2003 |
| 6661054 | Semiconductor device and method of fabricating the same A gate electrode is provided to fill up a trench while covering its opening. Assuming that WG represents the diameter (sectional width) of a head portion of the gate electrode located upward beyond a P-type base layer and an... | 12/09/2003 |
| 6660591 | Trench-gate semiconductor devices having a channel-accommodating region and their methods of manufacture Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. Thereby, the source region (13) and a contact window... | 12/09/2003 |
| 6656798 | Gate processing method with reduced gate oxide corner and edge thinning Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an active device area capped with a pad oxide layer bounded by one or more isolation trenches, prov... | 12/02/2003 |
| 6642581 | Semiconductor device comprising buried channel region A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gat... | 11/04/2003 |
| 6638801 | Semiconductor device and its manufacturing method A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than... | 10/28/2003 |
| 6638825 | Method for fabricating a high voltage device A high voltage device and a method for fabricating the same are disclosed, which improves voltage-resistant characteristics to protect against high voltage applied to a gate electrode. The high voltage device includes a semiconductor substrate having firs... | 10/28/2003 |
| 6639276 | Power MOSFET with ultra-deep base and reduced on resistance A power semiconductor device formed of a substrate of a first conductivity type, an epitaxial layer of a first conductivity type formed on a surface of the substrate, a plurality of lightly doped spaced base regions of a second conductivity type formed to... | 10/28/2003 |
| 6635534 | Method of manufacturing a trench MOSFET using selective growth epitaxy A method of manufacturing a trench structure for a trench MOSFET, including the steps of providing a semiconductor substrate having a major surface, forming a dielectric pillar on the substrate major surface (the dielectric pillar extending substantially ... | 10/21/2003 |
| 6635540 | Method for using thin spacers and oxidation in gate oxides A method for forming a lightly doped drain (LDD) field effect transistor uses very thin first sidewall spacers over the gate sidewalls, in which annealing/oxidation of the sidewall spacers results in (a) the rounding of corner portions of the gate structu... | 10/21/2003 |
| 6635544 | Method of fabricating a high-voltage transistor with a multi-layered extended drain structure A method for fabricating a high-voltage transistor with an extended drain region includes forming an epitaxial layer on a substrate, the epitaxial layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair ... | 10/21/2003 |
| 6620691 | Semiconductor trench device with enhanced gate oxide integrity structure A method for making trench DMOS is provided that improves the breakdown voltage of the oxide layer in a device having at least a first trench disposed in the active region of the device and a second trench disposed in the termination region of the device.... | 09/16/2003 |
| 6621121 | Vertical MOSFETs having trench-based gate electrodes within deeper trench-based source electrodes Vertical MOSFETs include a semiconductor substrate having a plurality of semiconductor mesas therein that are separated by a plurality of deep stripe-shaped trenches. These stripe-shaped trenches extend in parallel and lengthwise across the substrate in a... | 09/16/2003 |
| 6620653 | Semiconductor device and method of manufacturing the same A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is ... | 09/16/2003 |
| 6613633 | Method for manufacturing a high power semiconductor device having a field plate extendedly disposed on a gate A method to fabricate a high voltage transistor of a smart power device is discussed. The method includes forming a well of first conductivity in a substrate of second conductivity; forming a drift layer of the second conductivity in the well; forming a s... | 09/02/2003 |
| 6611031 | Semiconductor device and method for its manufacture A semiconductor device is disclosed including an insulated gate field effect transistor (IGFET) having a gate insulating layer (2), a gate electrode (3), and a source-drain layer (5). The IGFET may include a bird's beak insulating film (4) in a region in ... | 08/26/2003 |
| 6605860 | Semiconductor structures and manufacturing methods A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallograph... | 08/12/2003 |
| 6593175 | Method of controlling a shape of an oxide layer formed on a substrate A method of forming an oxide layer on a substrate comprises deposition of a mask layer with an opening for defining the area where the oxide layer is to be formed, and an ion implantation step performed with a tilt angle so as to obtain a varying ion conc... | 07/15/2003 |
| 6551900 | Trench gate oxide formation method A method for improving gate oxide thinning issue at trench corners is disclosed. The method comprises steps as follows. Firstly, a silicon substrate having a trench therein is provided. HDPCVD technology to form a first oxide layer on the sidewall and the... | 04/22/2003 |
| 6544873 | Methods of fabricating integrated circuit field effect transistors including multilayer gate electrodes having narrow and wide conductive layers An integrated circuit field effect transistor includes a multilayer gate electrode having a first conductive layer and a second conductive layer on the first conductive layer, wherein the second conductive layer is wider than the first conductive layer. T... | 04/08/2003 |
| 6534823 | Semiconductor device A semiconductor body has source and drain regions (4 and 5; 4' and 5') spaced apart by a body region (6; 6') and a drain drift region (50; 50') and both meeting the same surface (3a) of the semiconductor body. An insulated gate structure (7; 70'; 700) is ... | 03/18/2003 |
| 6531410 | Intrinsic dual gate oxide MOSFET using a damascene gate process Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as... | 03/11/2003 |
| 6528355 | Method for fabricating a trench MOS power transistor A method for fabricating a trench MOS transistor includes the step of at least partly filling the trench with a conductive material which is isolated from the inner surface of the trench by an insulating layer. The insulating layer has a layer thickness t... | 03/04/2003 |
| 6503786 | Power MOS device with asymmetrical channel structure for enhanced linear operation capability A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the devi... | 01/07/2003 |
| 6492676 | Semiconductor device having gate electrode in which depletion layer can be generated A semiconductor device including a first gate electrode having a first plane provided opposite to a first semiconductor region where a channel is to be formed with a first gate insulation film interposed therebetween; a second gate insulation film includi... | 12/10/2002 |
| 6489652 | Trench DMOS device having a high breakdown resistance A trench DMOS device having improved breakdown characteristics. The trench DMOS device has a gate oxide layer which has a substantially flattened thick portion in the bottom of the trench and which is relatively thinner on the sidewalls. In greater detail... | 12/03/2002 |
| 6465307 | Method for manufacturing an asymmetric I/O transistor According to one embodiment of the invention, a method of forming an asymmetric I/O transistor includes forming a first oxide layer outwardly from a semiconductor substrate, masking a first portion, less than a whole portion, of an I/O transistor region w... | 10/15/2002 |
| 6458639 | MOS transistor with stepped gate insulator A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drai... | 10/01/2002 |
| 6458664 | Method for fabricating a field-effect transistor having an anti-punch-through implantation region A simple method for fabricating a field-effect transistor having an anti-punch-through implantation region is provided. After the anti-punch-through implantation region is formed, a semiconductor substrate is locally oxidized by using a mask layer in orde... | 10/01/2002 |
