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| Number | Title | Issue Date |
| 7439595 | Field effect transistor having vertical channel structure A first SiO2 thin film, a tungsten gate electrode, and a second SiO2 thin film are selectively formed on a first n+-type GaN contact semiconductor layer in that order and in a multilayer film structure having the three layers, a stri... | 10/21/2008 |
| 7432557 | FinFET device with multiple channels A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxi... | 10/07/2008 |
| 7411241 | Vertical type nanotube semiconductor device A vertical type nanotube semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate a... | 08/12/2008 |
| 7397126 | Semiconductor device The present invention provides inhibiting an electrical leakage caused by anion migration. A trenched portion 15 is provided as ion migration-preventing zone between a source electrode 4 and a gate electrode 5. The trenched portion 15 is ... | 07/08/2008 |
| 7319255 | Semiconductor device including a metal gate electrode formed in a trench and method of forming thereof A semiconductor device including a transistor and a method of forming thereof are provided. The semiconductor device comprises a metal gate electrode. A lower portion of the metal gate electrode fills a channel trench formed at a predetermined region of a substrate,... | 01/15/2008 |
| 7317230 | Fin FET structure A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby r... | 01/08/2008 |
| 7301187 | High voltage field effect device and method Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more... | 11/27/2007 |
| 7262104 | Selective channel implantation for forming semiconductor devices with different threshold voltages Multiple semiconductor devices are formed with different threshold voltages. According to one exemplary implementation, first and second semiconductor devices are formed and doped differently, resulting in different threshold voltages for the first and second semico... | 08/28/2007 |
| 7259430 | Non-volatile memory device and method of manufacturing the same A non-volatile memory device includes a fin body protruded from a semiconductor substrate. The fin body has first and second side surfaces opposite to each other. An inner dielectric layer pattern is formed on an upper surface, and the first and second side surfaces... | 08/21/2007 |
| 7189660 | Method of producing insulator thin film, insulator thin film, method of manufacturing semiconductor device, and semiconductor device A method of producing an insulator thin film, for forming a thin film on a substrate by use of the atomic layer deposition process, includes a first step of forming a silicon atomic layer on the substrate and forming an oxygen atomic layer on the silicon atomic laye... | 03/13/2007 |
| 6696323 | Method of manufacturing semiconductor device having trench filled up with gate electrode In a semiconductor device, a p-type base region is provided in an n- -type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+ -type source region extends in the ... | 02/24/2004 |
| 6690047 | MIS transistor having a large driving current and method for producing the same In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drai... | 02/10/2004 |
| 6686245 | Vertical MOSFET with asymmetric gate structure A semiconductor fabrication process and structure in which a semiconductor channel structure (140) having first and second major surfaces perpendicular to a semiconductor substrate (102) is formed overlying and electrically isolated from the substrate (10... | 02/03/2004 |
| 6686626 | Source-down power transistor The invention relates to a source-down power transistor, in which narrow trenches filled with insulated polysilicon are provided between a source pillar and a drain pillar. Inversion channels form on the side walls of the trenches when a positive drain vo... | 02/03/2004 |
| 6670673 | Semiconductor device and method for manufacturing semiconductor device A first trench is formed in a surface of an n+ -type semiconductor substrate that forms a source region. A p-type base region, an n- -type drift region, and an n+ -type drain region are deposited in this order in the first... | 12/30/2003 |
| 6667213 | Method of fabricating a high-voltage transistor with a multi-layered extended drain structure A method for fabricating a high-voltage transistor with an extended drain region includes forming parallel arranged drift regions, each of which is interleaved with an insulating layer and a conducting layer that functions as a field plate. Source and bod... | 12/23/2003 |
| 6667227 | Trenched gate metal oxide semiconductor device and method A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region a drain region and a channel region.... | 12/23/2003 |
| 6664592 | Semiconductor device with groove type channel structure A semiconductor device includes a semiconductor substrate, a gate insulator film formed on a bottom surface and a side surface of a groove formed in the semiconductor substrate, a gate electrode having a lower portion buried in the groove on whose bottom ... | 12/16/2003 |
| 6661053 | Memory cell with trench transistor A memory cell includes a storage transistor having the following structure and being dimensioned to shorten program and erase times. A semiconductor body includes a top surface and a trench formed therein having walls joined by a curved bottom. A source z... | 12/09/2003 |
| 6642577 | Semiconductor device including power MOSFET and peripheral device and method for manufacturing the same First and second trenches are formed on an n+ type substrate at a power MOSFET formation region and a peripheral device formation region, respectively. An n- type epitaxial film, a p type epitaxial film, and an n+ type epi... | 11/04/2003 |
| 6639276 | Power MOSFET with ultra-deep base and reduced on resistance A power semiconductor device formed of a substrate of a first conductivity type, an epitaxial layer of a first conductivity type formed on a surface of the substrate, a plurality of lightly doped spaced base regions of a second conductivity type formed to... | 10/28/2003 |
| 6639274 | Semiconductor device A trench lateral MOSFET including a gate region where gate polysilicon is lead out to a substrate surface, and an active region where electric current is driven in a MOSFET operation, and with a trench width, in the gate region Wg, being narrower than a t... | 10/28/2003 |
| 6635544 | Method of fabricating a high-voltage transistor with a multi-layered extended drain structure A method for fabricating a high-voltage transistor with an extended drain region includes forming an epitaxial layer on a substrate, the epitaxial layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair ... | 10/21/2003 |
| 6633064 | Compensation component with improved robustness The compensation component is formed with compensation regions in a semiconductor between two electrodes. By varying the second field and/or the first field, a location of a maximum field strength is displaced into the center of the compensation regions b... | 10/14/2003 |
| 6630698 | High-voltage semiconductor component The invention relates to a high-voltage semiconductor component comprising semiconductor areas (4, 5) of alternating, different conductivity types which are arranged in a semiconductor body in an alternating manner. In the semiconductor body said semicond... | 10/07/2003 |
| 6624470 | Semiconductor device and a method for manufacturing same A semiconductor device, and method for manufacturing the same, manufactured by a simpler process, compared to a conventional trench lateral power MOSFET for a withstand voltage of 80 V, having a smaller device pitch and lower on-resistance per unit area a... | 09/23/2003 |
| 6617640 | Field-effect-controllable semiconductor configuration with a laterally extending channel zone A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first conductivity type, a channel zone of the first conductivity type, and at least one control electro... | 09/09/2003 |
| 6573145 | Process for producing an MOS field effect transistor with a recombination zone A process having a robust process sequence for producing an MOS field effect transistor having a horizontal buried gate formed of polysilicon and a recombination zone provided at the surface of the transistor includes the steps of producing the horizontal... | 06/03/2003 |
| 6559502 | Semiconductor device A semiconductor body has source and drain regions (4 and 5) spaced apart by a body region (6) and both meeting a surface (3a) of the semiconductor body. A gate structure (7) is provided within a trench (8) for controlling a conduction channel in a conduct... | 05/06/2003 |
| 6555872 | Trench gate fermi-threshold field effect transistors Field effect transistors include a semiconductor substrate of first conductivity type having a surface. A tub region of second conductivity type is in the semiconductor substrate at the surface and extends into the semiconductor substrate a first depth fr... | 04/29/2003 |
| 6548859 | MOS semiconductor device and method of manufacturing the same The object of the present invention is to suppress a short channel effect on a threshold voltage. A channel region 5, a pair of source-drain regions and an isolating film 2 having a trench isolation structure are selectively formed in a main surface of a ... | 04/15/2003 |
| 6545327 | Semiconductor device having different gate insulating films with different amount of carbon A manufacturing method produces a semiconductor IC device which can maintain a low power consumption for electronic circuits and form gate-isolation layers of different thicknesses without increasing the manufacturing cost. The semiconductor IC device has... | 04/08/2003 |
| 6515319 | Field-effect-controlled transistor and method for fabricating the transistor An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the sem... | 02/04/2003 |
| 6515338 | Semiconductor device and manufacturing method therefor A method of manufacturing semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a firs... | 02/04/2003 |
| 6515348 | Semiconductor device with FET MESA structure and vertical contact electrodes A semiconductor device comprises one or more field effect devices (FD) having source and drain regions (5 and 6) spaced apart by a body region (3a). A gate structure (7a, 7b), preferably in a trench (4), controls a conduction channel in a portion (3b) of ... | 02/04/2003 |
| 6429148 | Anisotropic formation process of oxide layers for vertical transistors The method of the present invention forms a thin oxide layer on the circumferential wall of a recess in a trench and, at the same time, forms a thick oxide layer on the bottom surface of the recess. The thick oxide layer serves as the trench top oxide and... | 08/06/2002 |
| 6368911 | Method for manufacturing a buried gate A method of manufacturing buried gates by performing two trench-forming operations. The method includes forming a first trench in a substrate, and then forming a dielectric layer over the substrate and the interior surface of the first trench. Next, condu... | 04/09/2002 |
| 6355532 | Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET A short vertical channel, dual-gate, CMOS FET is fabricated by forming a plurality of channel segments in a starting material that extend longitudinally between source and drain areas. The channel segments are laterally separated from one another by space... | 03/12/2002 |
| 6323524 | Semiconductor device having a vertical active region and method of manufacture thereof A semiconductor device and method of manufacture thereof is provided. According to one embodiment, a semiconductor device is formed by forming a trench within a substrate. An oxide layer is formed within the trench and portions of the oxide layer are remo... | 11/27/2001 |
| 6319777 | Trench semiconductor device manufacture with a thicker upper insulating layer In the manufacture of semiconductor devices that have an electrode (11,41) in an insulated trench (20), for example a trench-gate MOSFET, process steps are performed to line the trench walls with a lower insulating layer (21) in a lower part of the trench... | 11/20/2001 |
