Quotables
"The idea that cavalry will be replaced by these iron coaches is absurd. It is little short of treasonous."
Aide-de-camp to Field Marshal Haig ; At a tank demonstration, 1916
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7439134 | Method for process integration of non-volatile memory cell transistors with transistors of another type A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method inc... | 10/21/2008 |
| 7436018 | Discrete trap non-volatile multi-functional memory device A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate ... | 10/14/2008 |
| 7432561 | Non-volatile semiconductor memory and method for manufacturing a non-volatile semiconductor memory An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diff... | 10/07/2008 |
| 7432547 | Non-volatile memory device with improved data retention and method therefor A semiconductor device (30) comprises an underlying insulating layer (34), an overlying insulating layer (42) and a charge storage layer (36) between the insulating layers (34, 42). The charge storage layer (36) and the over... | 10/07/2008 |
| 7423314 | Semiconductor memory device and method for the same A semiconductor substrate 20, a gate electrode 34, first and second impurity diffusion regions 24a and 24b, first and second variable-resistance regions 22a, 22b, first and second main electrodes ... | 09/09/2008 |
| 7423313 | NAND-type semiconductor storage device and method for manufacturing same According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate ... | 09/09/2008 |
| 7419870 | Method of manufacturing a flash memory device Provided is a method of manufacturing a flash memory device. In the method, after forming a cell string and source/drain selection transistors, it forms a first oxide film in which a sidewall oxide film and a buffering oxide film are stacked, a nitride film, and a s... | 09/02/2008 |
| 7411243 | Nonvolatile semiconductor device and method of fabricating the same A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface... | 08/12/2008 |
| 7408219 | Nonvolatile semiconductor memory device In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conduct... | 08/05/2008 |
| 7405440 | Nonvolatile semiconductor memory A nonvolatile semiconductor memory on a semiconductor chip includes: a cell array region configured with a memory cell transistor having a first metallic salicide film, a first control gate electrode electrically coupled with the first metallic salicide film, and a ... | 07/29/2008 |
| 7405124 | Fabricating method of non-volatile memory A method for fabricating a non-volatile memory is described. A substrate having isolation structures is provided. These isolation structures protrude from the substrate, and a first mask layer is formed on the substrate between the isolation structures. A second mas... | 07/29/2008 |
| 7397079 | Non-volatile memory device and methods of forming the same A non-volatile memory device includes a control gate electrode disposed on a substrate with a first insulation layer interposed therebetween and a floating gate disposed in a hole exposing substrate through the control gate electrode and the first insulation layer. ... | 07/08/2008 |
| 7391076 | Non-volatile memory cells A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode pr... | 06/24/2008 |
| 7391072 | Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which h... | 06/24/2008 |
| 7387933 | EEPROM device and method of fabricating the same A memory device comprises a semiconductor substrate of a first conductive type, a memory transistor, a select transistor, a floating junction region, a common source region, and a bit line junction region. The floating junction region is formed of a second conductiv... | 06/17/2008 |
| 7372098 | Low power flash memory devices A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and ... | 05/13/2008 |
| 7372096 | Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which h... | 05/13/2008 |
| 7372097 | Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which h... | 05/13/2008 |
| 7368346 | Method for forming gate structure in flash memory device Device isolation insulation layers passing through an insulation layer and a substrate, are formed, and a portion of them is removed. The insulation layer is removed. A gate oxide layer and a first conductive layer sequentially formed over the device isolation insul... | 05/06/2008 |
| 7361554 | Multi-bit non-volatile memory device, method of operating the same, and method of manufacturing the multi-bit non-volatile memory device Disclosed are a multi-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the multi-bit non-volatile memory device may be formed on a semiconductor substrate may inclu... | 04/22/2008 |
| 7355236 | Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof. The non-volatile floating gate memory cell comprises a semiconductor substrate of a first conductivity type. A first region of a second conductivity type different... | 04/08/2008 |
| 7351629 | Method of forming non-volatile memory device A non-volatile memory device comprises an active region disposed in a predetermined region of a semiconductor substrate, a selection gate electrode crossing over the active region, and a floating gate electrode disposed on the active region parallel to the selection... | 04/01/2008 |
| 7339231 | Semiconductor device and an integrated circuit card There is provided a technology capable of enhancing reliability in rewrite of storage information in a nonvolatile memory while checking an increase in area of a memory array thereof. With a memory array configuration, individual bit lines are connected to two memor... | 03/04/2008 |
| 7338866 | Strapping word lines of NAND memory devices Conductive straps are connected to a subset of word lines of a memory device. Alternatively, first conductive straps are respectively connected only to first portions of first word lines of a memory device, and second conductive straps are respectively connected onl... | 03/04/2008 |
| 7335937 | Nonvolatile semiconductor memory In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1... | 02/26/2008 |
| 7323741 | Semiconductor nonvolatile memory device A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in par... | 01/29/2008 |
| 7323744 | Semiconductor device and fabrication method therefor A semiconductor device includes an ONO film (17) formed on a semiconductor substrate (15), a first gate (14), the first gate (14) formed on the ONO film (17), a source (10) and a drain (12) provided at both sides of t... | 01/29/2008 |
| 7312498 | Nonvolatile semiconductor memory cell and method of manufacturing the same A stacked-gate structure includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on a semiconductor substrate. The inter-electrode insulation film has a three-layer structure th... | 12/25/2007 |
| 7309892 | Semiconductor element and semiconductor memory device using the same A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so ... | 12/18/2007 |
| 7304344 | Integrated circuit having independently formed array and peripheral isolation dielectrics The invention comprises a method of forming an integrated circuit, the method comprising: (1) forming a first dielectric layer disposed outwardly from a semiconductor substrate; (2) forming a first intermediate structure outwardly from the a dielectric layer, the fi... | 12/04/2007 |
| 7285819 | Nonvolatile storage array with continuous control gate employing hot carrier injection programming An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the cha... | 10/23/2007 |
| 7282758 | Method of fabricating a floating gate for a nonvolatile memory A method of fabricating a gate structure (such as a floating gate) of a nonvolatile (e.g., flash) memory is described. After a polysilicon layer and a mask layer (e.g., silicon nitride) are formed on a semiconductor substrate, the silicon nitride layer is patterned ... | 10/16/2007 |
| 7271433 | High-density single transistor vertical memory gain cell A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away f... | 09/18/2007 |
| 7268389 | Nonvolatile semiconductor memory A nonvolatile semiconductor memory device includes diffusion layers formed in a semiconductor substrate, a gate insulating film formed on at least a portion of a channel region between the diffusion layers in the semiconductor substrate, and a control gate formed on... | 09/11/2007 |
| 7268064 | Method of forming polysilicon layer in semiconductor device Disclosed herein is a method of forming a polysilicon film of a semiconductor device. Upon deposition process of a polysilicon film, the inflow of a gas is reduced to 150 sccm to 250 sccm to control abnormal deposition depending upon excessive inflow of the gas. Acc... | 09/11/2007 |
| 7268387 | Semiconductor device and an electronic device The present invention provides a semiconductor nonvolatile memory in which writing or erasing of storing information can be carried out at a high speed with low consumption power and in which dispersion width of a threshold voltage after writing or erasing is very n... | 09/11/2007 |
| 7265411 | Non-volatile memory having multiple gate structure In one embodiment, a semiconductor device comprises an insulated floating gate disposed on a semiconductor substrate, an insulated program gate formed at least on a side surface of the floating gate, and an insulated erase gate disposed adjacent the floating gate. | 09/04/2007 |
| 7262458 | Semiconductor memory device and portable electronic apparatus A semiconductor memory device includes: a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type oppos... | 08/28/2007 |
| 7259430 | Non-volatile memory device and method of manufacturing the same A non-volatile memory device includes a fin body protruded from a semiconductor substrate. The fin body has first and second side surfaces opposite to each other. An inner dielectric layer pattern is formed on an upper surface, and the first and second side surfaces... | 08/21/2007 |
| 7259067 | Method for manufacturing flash memory device The present invention relates to a method for manufacturing a flash memory device. A plurality of conductive layers and dielectric layers are etched in a single etch apparatus, thus forming a control gate and a floating gate. In a gate formation process in which a t... | 08/21/2007 |
