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| Number | Title | Issue Date |
| 7205657 | Complimentary lateral nitride transistors A semiconductor device which includes a laterally extending stack of laterally adjacent conductive semiconductor regions formed over a support surface of a substrate, and a method for fabricating the device. ... | 04/17/2007 |
| 7126193 | Metal-oxide-semiconductor device with enhanced source electrode An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semicond... | 10/24/2006 |
| 6696323 | Method of manufacturing semiconductor device having trench filled up with gate electrode In a semiconductor device, a p-type base region is provided in an n- -type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+ -type source region extends in the ... | 02/24/2004 |
| 6677641 | Semiconductor structure with improved smaller forward voltage loss and higher blocking capability A semiconductor device is disclosed. The semiconductor device includes one or more charge control electrodes a plurality of charge control electrodes. The one or more charge control electrodes may control the electric field within the drift region of a se... | 01/13/2004 |
| 6677212 | Elevated source/drain field effect transistor and method for making the same A gate oxide film (23), a gate electrode (24) and a gate cap insulating film (25) are stacked on an active region of a p-type semiconductor substrate (21), and an insulating side wall (29) is formed, followed by BF2 ion implantation. Thus, a su... | 01/13/2004 |
| 6674135 | Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain re... | 01/06/2004 |
| 6670253 | Fabrication method for punch-through defect resistant semiconductor memory device A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting ... | 12/30/2003 |
| 6667516 | RF LDMOS on partial SOI substrate In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, ... | 12/23/2003 |
| 6664163 | Low on-resistance trench lateral MISFET with better switching characteristics and method for manufacturing same A high-voltage and low on-resistance semiconductor device incorporates a trench structure that provides improved switching characteristics. In a preferred embodiment, a Trench Lateral Power MISFET is provided having a gate, channel and drift regions that ... | 12/16/2003 |
| 6639274 | Semiconductor device A trench lateral MOSFET including a gate region where gate polysilicon is lead out to a substrate surface, and an active region where electric current is driven in a MOSFET operation, and with a trench width, in the gate region Wg, being narrower than a t... | 10/28/2003 |
| 6633064 | Compensation component with improved robustness The compensation component is formed with compensation regions in a semiconductor between two electrodes. By varying the second field and/or the first field, a location of a maximum field strength is displaced into the center of the compensation regions b... | 10/14/2003 |
| 6624470 | Semiconductor device and a method for manufacturing same A semiconductor device, and method for manufacturing the same, manufactured by a simpler process, compared to a conventional trench lateral power MOSFET for a withstand voltage of 80 V, having a smaller device pitch and lower on-resistance per unit area a... | 09/23/2003 |
| 6624045 | Thermal conducting trench in a seminconductor structure and method for forming the same The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a co... | 09/23/2003 |
| 6620663 | Self-aligned copper plating/CMP process for RF lateral MOS device A method of fabricating an RF lateral MOS device, comprising the following steps. A substrate having a gate oxide layer formed thereover is provided. A first layer of polysilicon is formed over the gate oxide layer. A second layer of material is formed ov... | 09/16/2003 |
| 6620667 | Method of making a HF LDMOS structure with a trench type sinker A method of forming an HF power device. The method includes forming a semiconductor layer as a first conductive type on a semiconductor substrate; etching the semiconductor layer forming a first trench; doping an impurity in the neighborhood of the first ... | 09/16/2003 |
| 6617640 | Field-effect-controllable semiconductor configuration with a laterally extending channel zone A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first conductivity type, a channel zone of the first conductivity type, and at least one control electro... | 09/09/2003 |
| 6605841 | Method for producing an electrode by means of a field effect controllable semiconductor component and field-effect-controllable semiconductor component A field-effect-controllable semiconductor component and a method for fabricating an electrode of the component includes a semiconductor body having a first zone of a first conduction type, a second zone of a second conduction type disposed above the first... | 08/12/2003 |
| 6541317 | Polysilicon doped transistor Steep concentration gradients are achieved in semiconductor device of small sizes by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates... | 04/01/2003 |
| 6518155 | Device structure and method for reducing silicide encroachment A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. ... | 02/11/2003 |
| 6506651 | Semiconductor device and manufacturing method thereof There are provide a semiconductor device capable of increasing the operating speed of MOS transistors and improving current driving capability, and a method of manufacturing such a semiconductor device. A semiconductor device comprises a silicon substrate... | 01/14/2003 |
| 6483158 | Semiconductor memory device and fabrication method therefor A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting ... | 11/19/2002 |
| 6440806 | Method for producing metal-semiconductor compound regions on semiconductor devices A method of making metal-semiconductor compound regions, such as silicide regions, includes forming a metal layer on a surface of a semiconductor device, performing a first annealing to form metal-semiconductor regions, and depositing additional metal wit... | 08/27/2002 |
| 6403482 | Self-aligned junction isolation Transistors having self-aligned dielectric layers under the source/drain contacts are formed by constructing transistors up to the LDD implant; etching STI oxide selective to Si and nitride to form a self-aligned contact recess; depositing an insulating l... | 06/11/2002 |
| 6373119 | Semiconductor device and method of manufacturing the same A semiconductor device including a trench element separation structure and adapted to a high degree of integration without having crystal defects produced in a semiconductor substrate, and a method of manufacturing the same. The semiconductor device inclu... | 04/16/2002 |
| 6352903 | Junction isolation In a bulk silicon process, an insulating layer is placed under the portion of the source and drain used for contacts, thereby reducing junction capacitance. The processing involves a smaller than usual transistor area that is not large enough to hold the ... | 03/05/2002 |
| 6346729 | Pseudo silicon on insulator MOSFET device A process for forming a MOSFET device, featuring a heavily doped source/drain region, isolated from a semiconductor substrate, via use of a thin silicon oxide layer, has been developed. After formation of a lightly doped source/drain region, an opening is... | 02/12/2002 |
| 6323506 | Self-aligned silicon carbide LMOSFET A lateral metal-oxide-semiconductor field effect transistor (LMOSFET) having a self-aligned gate, includes a first layer of SiC semiconductor material having a p-type conductivity, and a second layer of SiC semiconductor material having an n-type conducti... | 11/27/2001 |
| 6274894 | Low-bandgap source and drain formation for short-channel MOS transistors A transistor having source and drain regions which include lower-bandgap portions and a method for making the same are provided. A gate conductor is formed over a gate dielectric on a semiconductor substrate. The gate conductor is covered on all sides wit... | 08/14/2001 |
| 6222254 | Thermal conducting trench in a semiconductor structure and method for forming the same The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a co... | 04/24/2001 |
| 6222233 | Lateral RF MOS device with improved drain structure The lateral RF MOS device having a conducive plug in the source region and an oxide plug in the drain region is disclosed. The oxide plug in the drain region reduces the drain-source capacitance, improves the matching ability to the outside circuitry, and... | 04/24/2001 |
| 6180441 | Bar field effect transistor A field effect transistor is formed across a one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.... | 01/30/2001 |
| 6124614 | Si/SiGe MOSFET and method for fabricating the same The present invention relates to a metal silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel to effectively adjust threshold voltage. The transistor according to the present invention can solve the probl... | 09/26/2000 |
| 6121100 | Method of fabricating a MOS transistor with a raised source/drain extension A method of forming a MOS transistor. According to the method of the present invention, a pair of source/drain contact regions are formed on opposite sides of a gate electrode. After forming the pair of source/drain contact regions, semiconductor material... | 09/19/2000 |
| 6100147 | Method for manufacturing a high performance transistor with self-aligned dopant profile A process for manufacturing a high performance transistor with self-aligned dopant profile. The process involves forming a source/drain mask pattern on a substrate. With a first implant material, unmasked portions of the substrate are doped to form source... | 08/08/2000 |
| 6093612 | Metal oxide silicon field effect transistor (MOSFET) and fabrication method of same A Metal Oxide Silicon Field Effect Transistor (MOSFET) and method includes a gate electrode pattern formed over a gate insulation layer on a semiconductor substrate. A pair of first impurity regions are respectively formed in an upper side surface of the ... | 07/25/2000 |
| 6087706 | Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls A semiconductor integrated circuit with a transistor formed within an active area defined by side-walls of a shallow trench isolation region, and method of fabrication thereof, is described. A gate electrode is formed over a portion of the active area and... | 07/11/2000 |
| 6071783 | Pseudo silicon on insulator MOSFET device A process for forming a MOSFET device, featuring a heavily doped source/drain region, isolated from a semiconductor substrate, via use of a thin silicon oxide layer, has been developed. After formation of a lightly doped source/drain region, an opening is... | 06/06/2000 |
| 6072215 | Semiconductor device including lateral MOS element Disclosed is a semiconductor device including a lateral MOS element which comprises a p-type silicon substrate; a first semiconductor layer of an n-type constituting a drift region; a second semiconductor layer of the p-type selectively provided in the fi... | 06/06/2000 |
| 6064099 | Layout of well contacts and source contacts of a semiconductor device There is described a semiconductor device intended to increase a degree of integration of transistor without impairing a desired element characteristic. An n-type source region and an n-type drain region are formed in a p-well which acts as a substrate re... | 05/16/2000 |
| 6051472 | Semiconductor device and method of producing the same A semiconductor device of the present invention and using trench isolation includes contact holes. Spacers are formed on the shoulder portions of a device region exposed in the contact holes. To form the spacers, a silicon oxide film is formed and then et... | 04/18/2000 |
