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| Number | Title | Issue Date |
| 7405418 | Memory device electrode with a surface structure The invention relates to a memory device electrode, in particular for a resistively switching memory device, wherein the surface of the electrode is provided with a structure, in particular comprises one or a plurality of shoulders or projections, respectively. Furt... | 07/29/2008 |
| 7332811 | Integrated circuit interconnect A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrysta... | 02/19/2008 |
| 7326618 | Low OHMIC layout technique for MOS transistors A method of making a transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect the so... | 02/05/2008 |
| 7301239 | Wiring structure to minimize stress induced void formation A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n”... | 11/27/2007 |
| 7279744 | Control of hot carrier injection in a metal-oxide semiconductor device An MOS device is formed including a semiconductor layer of a first conductivity type, and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and secon... | 10/09/2007 |
| 7268067 | Semiconductor integrated circuit package having electrically disconnected solder balls for mounting Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., “dummy” solder balls, and are used to t... | 09/11/2007 |
| 7259430 | Non-volatile memory device and method of manufacturing the same A non-volatile memory device includes a fin body protruded from a semiconductor substrate. The fin body has first and second side surfaces opposite to each other. An inner dielectric layer pattern is formed on an upper surface, and the first and second side surfaces... | 08/21/2007 |
| 7220984 | Influence of surface geometry on metal properties The influence of surface geometry on metal properties is studied within the limit of the quantum theory of free electrons. It is shown that a metal surface can be modified with patterned indents to increase the Fermi energy level inside the metal, leading to decreas... | 05/22/2007 |
| 7170176 | Semiconductor device A technology for easily forming a multi-layer wiring structure that is fine and reliable. In the multi-layer wiring structure, the lower-layer wiring and the upper-layer wiring that are formed to sandwich an insulating layer are electrically connected to each other ... | 01/30/2007 |
| 7112855 | Low ohmic layout technique for MOS transistors The disclosure relates to a transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect... | 09/26/2006 |
| 7034358 | Vertical transistor, and a method for producing a vertical transistor The present invention relates to a method for producing a vertical transistor, and to a vertical transistor. A sacrificial gate oxide and a sacrificial gate electrode are used during the production of the vertical transistor to makes it possible to considerably redu... | 04/25/2006 |
| 6686625 | Field effect-controllable semiconductor component with two-directional blocking, and a method of producing the semiconductor component The semiconductor component can be controlled by the field effect and it blocks in both directions. The component has a semiconductor body with a first connecting zone, a second connecting zone and a channel zone formed between the first and the second co... | 02/03/2004 |
| 6387765 | Method for forming an extended metal gate using a damascene process A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, ... | 05/14/2002 |
| 6326273 | Method of fabricating a field effect transistor with trapezoidal shaped gate dielectric and/or gate electrode A gate structure of a field effect transistor is fabricated with a gate dielectric having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO2) (i.e., a high dielectric constant material) for higher thickne... | 12/04/2001 |
| 6303447 | Method for forming an extended metal gate using a damascene process A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, ... | 10/16/2001 |
| 6225674 | Semiconductor structure and method of manufacture A semiconductor structure (10) having device isolation structures (43, 44) and shielding structures (39, 40). The shielding structures (39, 40) are formed in a semiconductor material (11) and the device isolation structures (43, 44) are formed within the ... | 05/01/2001 |
| 6218223 | Process for producing electrode for semiconductor element and semiconductor device having the electrode A process is provided for fabricating a structure wherein the longitudinal direction of a base electrode and the longitudinal direction of an emitter electrode are the same. This structure is special and provides the advantage that, even if the element is... | 04/17/2001 |
| 5670819 | Semiconductor device with pad electrode An N- -type epitaxial layer is formed on a P-type semiconductor substrate. A P-type region is formed in the N- -type epitaxial layer. First and second N- -type layer islands, isolated by the P-type region, are formed in th... | 09/23/1997 |
| 5424572 | Spacer formation in a semiconductor structure A contact structure and a method for fabrication is disclosed for a semiconductor device that includes a plurality of semiconductor regions along the surface of the device, each region having a top surface and at least a sidewall surface, where a first pa... | 06/13/1995 |
| 5283454 | Semiconductor device including very low sheet resistivity buried layer A metal or silicide buried layer in MOS semiconductor devices provides a drain contact on the upper surface of the device with a greatly reduced resistance. The methods of manufacture include depositing the buried layer, rather than diffusing, so that int... | 02/01/1994 |
| 5233224 | Electrode having an improved configuration for a semiconductor element An electrode for semiconductor element to be directly connected to the semiconductor region of a semiconductor element is substantially shaped in a square column. When the length of one side of the surface in contact with the semiconductor region in said ... | 08/03/1993 |
| 5219784 | Spacer formation in a BICMOS device A contact structure and a method for fabrication is disclosed for a semiconductor device that includes a plurality of semiconductor regions along the surface of the device, each region having a top surface and at least a sidewall surface, where a first pa... | 06/15/1993 |
| 5168332 | Semiconductor device having salicide structure, method of manufacturing the same, and heating apparatus A semiconductor device including a semiconductor substrate of a first conductivity type. An insulative film and metal films are sequentially formed on the main top surface of the semiconductor substrate. Impurity diffusion layers of a second conductivity ... | 12/01/1992 |
| 5162263 | Semiconductor device having salicide structure, method of manufacturing the same, and heating apparatus A semiconductor device comprises a semiconductor substrate of a first conductivity type. An insulative film and metal films are sequentially formed on the main top surface of the semiconductor substrate. Impurity diffusion layers of a second conductivity ... | 11/10/1992 |
| 5155561 | Permeable base transistor having an electrode configuration for heat dissipation The base layer of a power permeable base transistor is formed as comb structures with grating teeth of the combs extending into active regions of semiconductor material. Extended active regions are separated by inactive regions over which collector contac... | 10/13/1992 |
| 5134448 | MOSFET with substrate source contact A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N+, N-, P-, N+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred... | 07/28/1992 |
| 5122856 | Semiconductor device A semiconductor device having a semiconductor layer, in which an active device such as a MOS or bipolar transistor in the front surface area of the semiconductor layer, and a device for communicating the front and rear surfaces of the semiconductor layer ... | 06/16/1992 |
| 5095351 | Semiconductor device having bipolar transistor and method of producing the same A semiconductor device has a base substrate made of a conductor or a semiconductor, an insulator layer formed on the base substrate, an active layer made of a semiconductor and formed on the insulator layer, where the active layer at least has a bipolar t... | 03/10/1992 |
| 5073815 | Semiconductor substrate and method for producing the same A semiconductor substrate that comprises: a base plate member made from a dielectric material; a refractory metal film covering at least a part of the base plate member; a single crystal semiconductor film formed on the refractory metal film; and an impur... | 12/17/1991 |
| 5034346 | Method for forming shorting contact for semiconductor which allows for relaxed alignment tolerance A method is disclosed for forming a shorting contact for shorting P-type and N-type conductivity regions in a semiconductor together. In one embodiment of this method, the P-type region is substantially a square and is surrounded by the N-type region. A s... | 07/23/1991 |
| 5032882 | Semiconductor device having trench type structure A semiconductor device comprises a P type semiconductor substrate (1) with a trench (12) formed on a main surface thereof. An N type drain region (15a) is formed at the bottom surface portion of the trench (12). An insulating layer (19c) is formed on the ... | 07/16/1991 |
| 5023196 | Method for forming a MOSFET with substrate source contact A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N+, N-,P-, N+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred... | 06/11/1991 |
| 4972240 | Vertical power MOS transistor A vertical power MOS transistor, in which a gate oxide film is formed over partial areas of a semiconductor substrate having a first conductivity type, which functions as a drain, a channel region having a second conductivity type formed in the substrate,... | 11/20/1990 |
| 4951101 | Diamond shorting contact for semiconductors A diamond-shaped short contact overlapping two differing conductivity regions in a semiconductor. The shape and orientation providing maximum alignment tolerances for a given size of contact opening.... | 08/21/1990 |
| 4920393 | Insulated-gate field-effect semiconductor device with doped regions in channel to raise breakdown voltage An insulated-gate field-effect semiconductor device comprising a silicon substrate of a first conductivity type, heavily doped source and drain regions of a second conductivity type in the substrate, a plurality of island regions of the second conductivit... | 04/24/1990 |
| 4914501 | Vertical contact structure A compact vertical contact has lateral space requirements in the fabrication of semiconductor devices and is compatible with highly planarized processes. The contact is made from a foundation region having a top surface to an overlying layer separated fro... | 04/03/1990 |
| 4914050 | Semiconductor device and manufacturing method thereof A concave portion having a V-shaped cross section is formed in a contact region of a p-type silicon substrate. The contact region is defined by a hole formed in an insulative layer formed over the substrate. An n-type diffusion layer is formed in the subs... | 04/03/1990 |
| 4884121 | Semiconductor device A semiconductor device comprises a semiconductor substrate having a convex portion and at least one conductive interconnection layer formed over the substrate. The interconnection layer has a contact region to be electrically connected. The convex portion... | 11/28/1989 |
| 4882608 | Multilayer semiconductor device having multiple paths of current flow A multilayer semiconductor structure is disclosed having a plurality of conducting layers separated by a barrier layer. A common contact extends from an upper exposed surface to all the layers of the device and a surface contact extends from the upper sur... | 11/21/1989 |
| 4868636 | Power thyristor A power thyristor includes a semiconductor body having first and second main surfaces, the first main surface being planar; at least first and second metal electrodes disposed at least on the first main surface; the first electrode having a contact surfac... | 09/19/1989 |
