Bizarre Patents
A sealed crustless sandwich for providing a convenient sandwich without an outer crust which can be stored for long periods of time without a central filling from leaking outwardly.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7323391 | Substrate having silicon germanium material and stressed silicon nitride layer A method of fabricating a semiconductor device includes providing a region having doped silicon region on a substrate, and forming a silicon germanium material adjacent to the region on the substrate. A stressed silicon nitride layer is formed over at least a portio... | 01/29/2008 |
| 7199404 | Semiconductor substrate and semiconductor device using the same A semiconductor substrate used for fabricating vertical devices, such as vertical MOSFET, capable of maintaining low ON-stage resistance and of ensuring a necessary level of OFF-stage breakdown voltage is provided. A heavily-doped arsenic layer of 0.5 to 3.0 μm thi... | 04/03/2007 |
| 6664590 | Circuit configuration for load-relieved switching A circuit configuration for load-relieved switching has a bridge circuit with at least two controllable power switches, whose controlled paths are arranged in series with one another and between a first and a second supply potential. The circuit configura... | 12/16/2003 |
| 6630697 | GaAs single crystal as well as method of producing the same, and semiconductor device utilizing the GaAs single crystal By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer si reduced, ther... | 10/07/2003 |
| 6610572 | Semiconductor device and method for manufacturing the same A semiconductor device is provided which can be manufactured even by using an inexpensive FZ wafer in a wafer process and still has a sharp inclination of a high impurity concentration in a high impurity concentration layer at the outermost portion of the... | 08/26/2003 |
| 6603189 | Semiconductor device with deliberately damaged layer having a shorter carrier lifetime therein A technique of improving a reverse recovery characteristic of a semiconductor device which solves a technical problem of breakdown voltage reduction which has conventionally caused in enhancing soft recover. To solve the technical problem, in a PN junctio... | 08/05/2003 |
| 6489187 | Method for setting the breakover voltage of a thyristor The effective doping profile of a finished thyristor is altered with helium ions radiated into a region provided for triggering the thyristor in such a way that the breakover voltage for overhead ignition is increased or reduced. Doping profile changes ma... | 12/03/2002 |
| 6483134 | Integrated circuits with immunity to single event effects The present invention is an electronic structure having a buffer layer with a short average carrier lifetime, at least about 1000 Å thick with an upper face, and an integrated circuit disposed over the upper face of the buffer layer, where this integrate... | 11/19/2002 |
| 6482681 | Hydrogen implant for buffer zone of punch-through non epi IGBT An IGBT is formed in a thin (less than 250 microns thick) float zone silicon wafer using a hydrogen implant to form an N+ buffer layer at the bottom of the wafer. A weak anode is formed on the bottom of the wafer. A single hydrogen implant, or ... | 11/19/2002 |
| 6475926 | Substrate for high frequency integrated circuits A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron par... | 11/05/2002 |
| 6465871 | Semiconductor switching device and method of controlling a carrier lifetime in a semiconductor switching device A semiconductor layer, through which a main current flows, is so structured that a carrier life time in the semiconductor layer is ununiform in accordance with a predetermined distribution of the carrier life time. Thus, turn OFF characteristics of a semi... | 10/15/2002 |
| 6465844 | Power semiconductor device and method of manufacturing the same A power semiconductor device has a plurality of U-shaped buried layers buried in a drift layer and made of either an insulating material or a semiconductor having a wider bandgap than that of the semiconductor of the drift layer. The ratio of the product ... | 10/15/2002 |
| 6420775 | Compound semiconductor device having an ion implanted defect-rich layer for improved backgate effect suppression A compound semiconductor device having improved backgate voltage resistance characteristics. To improve the backgate voltage resistance of a compound semiconductor device having field effect transistors on a main surface of a semi-insulating substrate, bo... | 07/16/2002 |
| 6417526 | Semiconductor device having a rectifying junction and method of manufacturing same The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller dop... | 07/09/2002 |
| 6414373 | Semiconductor device and method of fabricating the same A high-resistance substrate with good RF characteristics, which has an interstitial oxygen concentration ([Oi]) of 8E17 cm-3 or less, an oxygen precipitate density ([BMD]) of 1E8 cm-3 or more, and a substrate resistivity of 500 Ω.mu... | 07/02/2002 |
| 6407444 | Single event upset hardening of a semiconductor device using a buried electrode A semiconductor device includes a substrate such as indium phosphide having a trap density which increases with increasing distance from a top surface of the substrate, so that the electrical conductivity of the substrate increases with increasing distanc... | 06/18/2002 |
| 6404037 | Insulated gate bipolar transistor An insulated gate bipolar transistor having a collector electrode 3, an emitter region 6 and a base region 4 formed between the collector electrode and the emitter region, further including a channel stop region 17 spaced from the emitter region and elect... | 06/11/2002 |
| 6403989 | Semiconductor device, method of manufacturing same, and circuit provided with such a device The invention relates to a semiconductor device (10) comprising a semiconductor body (11) including, in succession, a first and a second semiconductor region (1, 2) of a first conductivity type having, respectively, a high and a low doping concentration, ... | 06/11/2002 |
| 6395653 | Semiconductor wafer with crystal lattice defects, and process for producing this wafer A semiconductor wafer has a front side 1, a back side 2, a top layer 3, a bottom layer 4, an upper inner layer 5 lying beneath the top layer 3, an lower inner layer 6 lying above the bottom layer 4, a central region 7 between the layers 5 and 6, and an un... | 05/28/2002 |
| 6376859 | Variable porosity porous silicon isolation Varying the porosity through the thickness of a porous silicon layer allows conflicting needs to be met by the same layer: a low porosity surface layer allows a high-quality epitaxial layer of silicon to be grown, or can provide structural support, while ... | 04/23/2002 |
| 6373079 | Thyristor with breakdown region The thyristor is based on a semiconductor body with an anode-side base zone of the first conductivity type and one or more cathode-side base zones of the opposite, second conductivity type. Anode-side and cathode-side emitter zones are provided, and at le... | 04/16/2002 |
| 6365478 | Solid state electronic device fabrication using crystalline defect control A solid state electronic device (40) comprising a substrate (30) and layers (32 and 34) is fabricated to control the formation of crystalline defects to control at least one characteristic of the device, such as current gain beta. The formation of crystal... | 04/02/2002 |
| 6351024 | Power semiconductor diode A semiconductor body including a first surface, a second surface, and a base doping for electrical conductivity. A first doped region is on the first surface and a second doped is on the second surface. The two doped regions are doped with opposites signs... | 02/26/2002 |
| 6297523 | GaAs single crystal as well as method of producing the same, and semiconductor device utilizing the same By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, ther... | 10/02/2001 |
| 6294804 | GaAs single crystal as well as method of producing the same, and semiconductor device utilizing the GaAs single crystal By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, ther... | 09/25/2001 |
| 6252259 | Semiconductor switching device having different carrier lifetimes between a first portion serving as a main current path and the remaining portion of the device A semiconductor layer, through which a main current flows, is so structured that a carrier life time in the semiconductor layer is uniform in accordance with a predetermined distribution of the carrier life time. Thus, turn OFF characteristics of a semico... | 06/26/2001 |
| 6239450 | Negative differential resistance device based on tunneling through microclusters, and method therefor A solid state electronic device exhibiting negative differential resistance is fabricated by depositing a thin layer of amorphous silicon on a single crystal substrate, doped N+. The amorphous silicon is simultaneously crystallized and oxidized... | 05/29/2001 |
| 6228694 | Method of increasing the mobility of MOS transistors by use of localized stress regions A method of modifying the mobility of a transistor. First, a substance is implanted into a substrate. The substrate is then annealed such that the implanted substance forms at least one void in the substrate. Then, a transistor is formed on the substrate.... | 05/08/2001 |
| 6222252 | Semiconductor substrate and method for producing the same A semiconductor substrate is provided which can efficiently exhibit intrinsic gettering (IG) effect, is less likely to cause slipping or dislocation, and causes no significant lowering in mechanical strength. The semiconductor substrate has bulk micro def... | 04/24/2001 |
| 6218683 | Diode The present invention relates to a diode, and has an object to simultaneously implement a high di/dt capability, a low reverse recovery loss and a low forward voltage and to suppress generation of voltage oscillation. In order to achieve the above-mention... | 04/17/2001 |
| 6204153 | Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device A fabrication process and transistor are described in which a transistor having decreased susceptibility to punchthrough and increased resistance to impurity diffusion is formed. One or more argon doped silicon epitaxial layers are formed superjacent a se... | 03/20/2001 |
| 6198115 | IGBT with reduced forward voltage drop and reduced switching loss The boundary between the P type silicon base and N+ buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.... | 03/06/2001 |
| 6183857 | Substrate for high frequency integrated circuits A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron par... | 02/06/2001 |
| 6168981 | Method and apparatus for the localized reduction of the lifetime of charge carriers, particularly in integrated electronic devices A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in th... | 01/02/2001 |
| 6165872 | Semiconductor device and its manufacturing method A denuded zone DZ least liable to generate defects is formed in a surface layer zone 12 of a semiconductor wafer 10. In an inner layer zone 18 of the semiconductor wafer 10, micro defects BMD for gettering of impurity metal are made. In the inner layer zo... | 12/26/2000 |
| 6143632 | Deuterium doping for hot carrier reliability improvement A semiconductor device having reduced hot carrier degradation is achieved by doping the semiconductor substrate and gate oxide with deuterium. A conventional semiconductor device is formed with sequentially deposited metal layers and dielectric layers and... | 11/07/2000 |
| 6114223 | Gettering regions and methods of forming gettering regions within a semiconductor wafer In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, ... | 09/05/2000 |
| 6111325 | Gettering regions and methods of forming gettering regions within a semiconductor wafer In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, ... | 08/29/2000 |
| 6100575 | Semiconductor switching device having different carrier lifetimes between a first portion serving as a main current path and the remaining portion of the device A semiconductor layer, through which a main current flows, is so structured that a carrier life time in the semiconductor layer is ununiform in accordance with a predetrmined distribution of the carrier life time. Thus, turn OFF characteristics of a semic... | 08/08/2000 |
| 6093955 | Power semiconductor device A semiconductor device having two or more p-n junctions, being in particular a bipolar transistor or a thyristor. The device has an gold ion implant in a region of the device between two of or the two p-n junctions, which region is the base in the case of... | 07/25/2000 |
