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...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
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| Number | Title | Issue Date |
| 7432551 | SOI semiconductor device including a guard ring region An object is to increase the amount of substrate noise absorbed in a guard ring, and to prevent a malfunction caused by the substrate noise in a semiconductor device including an SOI substrate provided with the guard ring. Then, there is provided a semiconductor dev... | 10/07/2008 |
| 7400016 | Semiconductor device realizing characteristics like a SOI MOSFET In a semiconductor device, source/drain layers have a low resistivity region and an extension region extending from the low resistivity region toward the channel region. The extension regions are lower in impurity concentration and shallower in depth than the low re... | 07/15/2008 |
| 7279767 | Semiconductor structure with high-voltage sustaining capability and fabrication method of the same A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to th... | 10/09/2007 |
| 7067880 | Transistor gate structure The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate co... | 06/27/2006 |
| 6703663 | CMOS device using additional implant regions to enhance ESD performance and device manufactured thereby A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with s... | 03/09/2004 |
| 6690060 | Field effect transistor and method of fabricating the same by controlling distribution condition of impurity region with implantation of additional ion A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide ... | 02/10/2004 |
| 6680224 | Methods of forming and operating field effect transistors having gate and sub-gate electrodes Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the chan... | 01/20/2004 |
| 6677208 | Transistor with bottomwall/sidewall junction capacitance reduction region and method A method of fabricating a transistor comprises forming a gate structure outwardly of a semiconductor substrate, wherein the gate structure comprises a gate, a gate insulator and sidewalls and forming source region and a drain region in the substrate using... | 01/13/2004 |
| 6677212 | Elevated source/drain field effect transistor and method for making the same A gate oxide film (23), a gate electrode (24) and a gate cap insulating film (25) are stacked on an active region of a p-type semiconductor substrate (21), and an insulating side wall (29) is formed, followed by BF2 ion implantation. Thus, a su... | 01/13/2004 |
| 6677210 | High voltage transistors with graded extension High voltage transistors with high breakdown voltages are provided. These high voltage transistors are formed with graded drain extension regions. The concentration of charge carriers increases farther away from the gate across each drain extension region... | 01/13/2004 |
| 6674130 | High performance PD SOI tunneling-biased MOSFET A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made s... | 01/06/2004 |
| 6667216 | Semiconductor device and method of fabricating the same A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substra... | 12/23/2003 |
| 6664600 | Graded LDD implant process for sub-half-micron MOS devices A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and d... | 12/16/2003 |
| 6660605 | Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss Methods are discussed for forming a transistor comprising a source/drain region having both a graded HDD portion and a sharp HDD portion in a semiconductor substrate. The method comprises a dual diffusion process, wherein a gate structure is provided over... | 12/09/2003 |
| 6649460 | Fabricating a substantially self-aligned MOSFET The present invention includes methods and structures for forming at least a substantially self-aligned MOSFET. According to the present invention, a method of fabricating a semiconductor device includes providing a substrate; providing first materials (s... | 11/18/2003 |
| 6642122 | Dual laser anneal for graded halo profile Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphiz... | 11/04/2003 |
| 6642581 | Semiconductor device comprising buried channel region A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gat... | 11/04/2003 |
| 6639277 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 10/28/2003 |
| 6633065 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 10/14/2003 |
| 6630385 | MOSFET with differential halo implant and annealing strategy A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of app... | 10/07/2003 |
| 6630386 | CMOS manufacturing process with self-amorphized source/drain junctions and extensions A method of manufacturing an integrated circuit may include the steps of annealing a gate structure and a halo section disposed over a substrate using a first temperature, implanting dopants to form drain and source regions, and annealing drain and source... | 10/07/2003 |
| 6624045 | Thermal conducting trench in a seminconductor structure and method for forming the same The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a co... | 09/23/2003 |
| 6624455 | Semiconductor device and method of manufacturing the same including drain pinned along channel width In a semiconductor device, pining regions 105 are disposed along the junction portion of a drain region 102 and a channel forming region 106 locally in a channel width direction. With this structure, because the spread of a depletion layer from a drain si... | 09/23/2003 |
| 6600200 | MOS transistor, method for fabricating a MOS transistor and method for fabricating two complementary MOS transistors A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 1017 cm-3 is disposed on a... | 07/29/2003 |
| 6597044 | Semiconductor device having a charge removal facility for minority carriers The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for example the... | 07/22/2003 |
| 6579770 | Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled po... | 06/17/2003 |
| 6573562 | Semiconductor component and method of operation A semiconductor component includes a semiconductor substrate (110) having first and second portions (111, 112) with a first conductivity type, a transistor (120) at least partially located in the semiconductor substrate, and a switching circuit (150, 350,... | 06/03/2003 |
| 6570219 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 05/27/2003 |
| 6563176 | Asymmetrical semiconductor device for ESD protection An asymmetrical ESD protection device and a method of production thereof are provided. A source region and a drain region are formed in a substrate. A gate is formed over the substrate between the drain and source regions. A compensating implant is formed... | 05/13/2003 |
| 6559016 | Method of manufacturing low-leakage, high-performance device A method of manufacturing a low-leakage, high-performance device. A substrate having a gate electrode thereon is provided. A lightly doped, high-energy implantation is conducted to form a lightly doped source/drain terminal in the substrate. An offset spa... | 05/06/2003 |
| 6548866 | Field effect transistor with reduced narrow channel effect In a field effect transistor, an element isolation trench is formed around the element region on the major surface of a silicon substrate. A gate electrode is formed on the major surface in the element region via a gate insulating film. Source and drain r... | 04/15/2003 |
| 6545326 | Method of fabricating semiconductor device An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position... | 04/08/2003 |
| 6544851 | Method of manufacturing a semiconductor device having a pocket implant in channel region In a method of manufacturing a semiconductor device comprising a semiconductor body (1) of a first conductivity type which is provided at a surface (2) with a transistor having a gate (28) insulated from a channel (13) provided at the surface (2) of the s... | 04/08/2003 |
| 6541341 | Method for fabricating MOS field effect transistor A method for fabricating a MOSFET includes a step of forming an isolation layer on an isolation region of a substrate, to thereby define an active region ion implanting As and P into the active region, and a step of forming a gate on the active region. An... | 04/01/2003 |
| 6524903 | Method of manufacturing a semiconductor device having two peaks in an impurity concentration distribution A method of manufacture of a semiconductor device calls for forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a first peak in impurity concentration distribution and another p type impurity l... | 02/25/2003 |
| 6525377 | Low threshold voltage MOS transistor and method of manufacture A low threshold voltage MOS device on a semiconductor substrate is disclosed. The substrate has an upper surface, and a first well region is disposed in said semiconductor substrate extending downwardly from the semiconductor substrate upper surface. The ... | 02/25/2003 |
| 6521962 | High voltage MOS devices A P channel high voltage metal oxide semiconductor device is described which is integrated in the same chip or wafer as standard P channel and N channel metal oxide semiconductor devices. The high voltage device has a lightly doped p- drift reg... | 02/18/2003 |
| 6518625 | Semiconductor device An n-type impurity layer is formed on a boundary portion between a source/drain and a field oxide film in a portion deeper than the source/drain. Even if a metal silicide layer such as a Co silicide layer extends into a portion under the field oxide film ... | 02/11/2003 |
| 6518105 | High performance PD SOI tunneling-biased MOSFET A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made s... | 02/11/2003 |
| 6509241 | Process for fabricating an MOS device having highly-localized halo regions A process for fabricating an MOS device having a highly-localized halo region includes the formation of a first halo region at a first surface of a silicon substrate, and a second halo region at a second surface of the silicon substrate. The second surfac... | 01/21/2003 |
