Class 257/E29.062 - With insulated gate (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E29.061. This subclass
No. of patents: 83
Last issue date: 09/30/2003

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Number	Title	Issue Date
6627955	Structure and method of MOS transistor having increased substrate resistance Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposi...	09/30/2003
6624451	High frequency field effect transistor with carrier extraction to reduce intrinsic conduction A field effect transistor (FET) is of the type which employs base biasing to depress the intrinsic contribution to conduction and reduce leakage current. It incorporates four successive layers (102 to 108): a p+ InSb base layer (102), a p+...	09/23/2003
6555894	Device with patterned wells and method for forming same In a semiconductor substrate having a top surface and a PN junction between a first region of one conductivity type formed by masked diffusion into a semiconductor from the surface and a second region of opposite conductivity type formed into a first port...	04/29/2003
6507058	Low threshold compact MOS device with channel region formed by outdiffusion of two regions and method of making same A compact metal oxide semiconductor (MOS) device has its channel region formed by the lateral extension of two high voltage (HV) regions. The two HV regions are implanted into a well region and, as a result of an annealing process, undergo outdiffusion an...	01/14/2003
6486510	Reduction of reverse short channel effects by implantation of neutral dopants A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and dr...	11/26/2002
6476412	Light emitting semiconductor device with partial reflection quantum-wave interference layers A semiconductor device is constituted by a quantum-wave interference layer with plural periods of a pair of a first layer W and a second layer B. The second layer B has wider band gap than the first layer W. Each thickness of the first layer W and the sec...	11/05/2002
6459141	Method and apparatus for suppressing the channeling effect in high energy deep well implantation The invention provides an improved well structure for electrically separating n-channel and p-channel MOSFETs. The invention first forms a shallow well in a substrate. A buried amorphous layer is then formed below the shallow well. A deep well is then for...	10/01/2002
6358815	Semiconductor device and method of manufacturing the same A semiconductor device comprises a silicon region (1) of the first conductivity type, a porous silicon layer (2) formed inside the silicon region (1) as a buried layer and a source region (3a) and a drain region (4a) of the second conductivity type differ...	03/19/2002
6352912	Reduction of reverse short channel effects by deep implantation of neutral dopants A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and dr...	03/05/2002
6346463	Method for forming a semiconductor device with a tailored well profile A method for forming a semiconductor device is provided. A base layer is provided. A first epitaxial layer having a first dopant at a first concentration is formed above the base layer. A second epitaxial layer having a second dopant at a second concentra...	02/12/2002
6335233	Method for fabricating MOS transistor A first conductive impurity ion is implanted into a semiconductor substrate to form a well area on which a gate electrode is formed. A first non-conductive impurity is implanted into the well area on both sides of the gate electrode to control a substrate...	01/01/2002
6316813	Semiconductor device with insulated gate transistor An insulated gate transistor comprises source regions; drain regions; channel regions provided between the source and drain regions; a gate electrode; and gate insulative film provided between the channel regions and the gate electrode. The device has a s...	11/13/2001
6291859	Integrated circuits A semiconductor integrated circuit comprises a substrate (1) of a first conduction type semiconductor material, an epitaxial layer (10) which is carried by the substrate (1) and which is of a second conduction type semiconductor material different to the ...	09/18/2001
6285072	Semiconductor device containing a porous structure and method of manufacturing the same A semiconductor device and a method of manufacturing the same are provided with a silicon region of a first conductivity type, a silicon layer including at least one cavity existing inside the silicon region as a buried layer, and a source/drain region of...	09/04/2001
6285057	Semiconductor device combining a MOSFET structure and a vertical-channel trench-substrate field effect device A semiconductor device that provides for substrate current exiting a MOSFET structure, and hence the performance thereof, to be independently and controllably tuned. The semiconductor device includes a semiconductor substrate of a first conductivity type,...	09/04/2001
6271551	Si-Ge CMOS semiconductor device To obtain a high mobility and a suitable threshold voltage in MOS transistors with channel dimensions in the deep sub-micron range, it is desirable to bury a strongly doped layer (or ground plane) in the channel region below a weakly doped intrinsic surfa...	08/07/2001
6262457	Method of producing a transistor structure Additional degrees of freedom are provided for optimizing the component properties by combining two doping profiles. The threshold voltage of NMOS or DMOS transistors can be set through the process parameters involved in the introduction and outward diffu...	07/17/2001
6242783	Semiconductor device with insulated gate transistor An insulated gate transistor comprises source regions; drain regions; channel regions provided between the source and drain regions; a gate electrode; and gate insulative film provided between the channel regions and the gate electrode. The device has a s...	06/05/2001
6213869	MOSFET-type device with higher driver current and lower steady state power dissipation A coupling capacitor is coupled between the gate and the body region of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The body region of the MOSFET is electrically isolated to form a floating body region. The capacitance of the coupling ca...	04/10/2001
6204153	Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device A fabrication process and transistor are described in which a transistor having decreased susceptibility to punchthrough and increased resistance to impurity diffusion is formed. One or more argon doped silicon epitaxial layers are formed superjacent a se...	03/20/2001
6194776	Semiconductor circuit device having triple-well structure in semiconductor substrate, method of fabricating the same, and mask device for fabrication of the same A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well reg...	02/27/2001
6188106	MOSFET having a highly doped channel liner and a dopant seal to provide enhanced device properties A fabrication process and integrated circuit are provided in which a transistor having increased resistance to punchthrough and decreased channel capacitance is formed. A liner layer is formed within the active region of a transistor to minimize punchthro...	02/13/2001
6175123	Semiconductor devices with quantum-wave interference layers A semiconductor device is constituted by a quantum-wave interference layer with plural periods of a pair of a first layer W and a second layer B. The second layer B has wider band gap than the first layer W. Each thickness of the first layer W and the sec...	01/16/2001
6153920	Process for controlling dopant diffusion in a semiconductor layer and semiconductor device formed thereby A semiconductor device having a carbon-containing region with an advantageous concentration profile is disclosed. The carbon is introduced into a region of the substrate and at a depth below the space-charge layer of the device and at a concentration such...	11/28/2000
6137148	NMOS transistor The NMOS transistor is provided with a semiconducting substrate (12) which is p-doped and comprises a top side (14), and with a first region (16) which is n-doped and placed into the substrate by diffusion from the top side (14) of the substrate (12). Fur...	10/24/2000
6097047	Ferroelectric semiconductor device, and ferroelectric semiconductor substrate A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) is manufactured from a substrate (11) that has a layer (14) of ferroelectric material sandwich...	08/01/2000
6087209	Formation of low resistance, ultra shallow LDD junctions employing a sub-surface, non-amorphous implant Ultra shallow, low resistance LDD junctions are achieved by forming an LDD implant generating an interstitial-rich section and forming a sub-surface, non-amorphous region generating a vacancy-rich region substantially overlapping the interstitial rich reg...	07/11/2000
6075259	Power semiconductor devices that utilize buried insulating regions to achieve higher than parallel-plane breakdown voltages Power semiconductor devices include a semiconductor substrate having a face thereon and a buried electrically insulating layer extending laterally in the semiconductor substrate and having an opening therein. A drift region of first conductivity type is a...	06/13/2000
6046475	Structure and method for manufacturing devices having inverse T-shaped well regions A structure for manufacturing devices having inverse T-shaped well regions, which are formed on a substrate, comprises a first doped region and second doped region which have higher impurity concentrations and two third doped regions which have a lower im...	04/04/2000
6043139	Process for controlling dopant diffusion in a semiconductor layer Diffusion of ion-implanted dopant is controlled by incorporating electrically inactive impurity in a semiconductor layer by at least one crystal growth technique....	03/28/2000
6005285	Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device A fabrication process and transistor are described in which a transistor having decreased susceptibility to punchthrough and increased resistance to impurity diffusion is formed. One or more argon doped silicon epitaxial layers are formed superjacent a se...	12/21/1999
5990531	Methods of making high voltage GaN-AlN based semiconductor devices and semiconductor devices made The present invention is directed to a technique for manufacturing semiconductor devices in which p type GaN is formed on a substrate and semi-insulating AlN is formed on the P type GaN with n type GaN formed on the p type GaN and partially below the AlN....	11/23/1999
5977602	Semiconductor device having an oxygen-rich punchthrough region extending through the length of the active region A semiconductor device having an oxygen-rich punchthrough region under the channel region, and a process for fabricating such a device are disclosed. In accordance with one embodiment, a semiconductor device is formed by forming an oxygen-rich punchthroug...	11/02/1999
5955745	Semiconductor device having SiGe spacer under an active layer A semiconductor device which does not allow production of leak current or a drop of the Early voltage and includes a diffused layer having a reduced depth. A silicon layer containing an impurity of a second conduction type is formed on a semiconductor sub...	09/21/1999
5950076	Methods of forming silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein A silicon carbide semiconductor device includes a silicon carbide substrate, an active layer in the substrate and a silicon carbide buried layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buri...	09/07/1999
5923987	Method for forming MOS devices with retrograde pocket regions and counter dopant regions at the substrate surface Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high dopant atom concentration (of the same conductivity type as the bulk region) abutting either the de...	07/13/1999
5914517	Trench-isolation type semiconductor device A semiconductor device and a method of manufacturing the same. The semiconductor device comprises: a semiconductor substrate; an impurity injection layer formed in a surface of the semiconductor substrate; and a trench formed in the impurity injection lay...	06/22/1999
5915164	Methods of making high voltage GaN-A1N based semiconductor devices The present invention is directed to a technique for manufacturing semiconductor devices in which p type GaN is formed on a substrate and semi-insulating AlN is formed on the P type GaN with n type GaN formed on the p type GaN and partially below the AlN....	06/22/1999
5891792	ESD device protection structure and process with high tilt angle GE implant A structure and method for fabricating an ESD device for FET transistors by forming a silicon germanium region 40 under a channel region 44 of a field effect transistor (FET). The silicon germanium region 40 comprises the base of a parasitic bipolar 200 t...	04/06/1999
5846847	Method of manufacturing a ferroelectric device A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) is manufactured from a substrate (11) that has a layer (14) of ferroelectric material sandwich...	12/08/1998

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Class 257/E29.062 - With insulated gate (EPO)