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| Number | Title | Issue Date |
| 6404015 | Semiconductor device The invention relates to a SOI deep depletion MOS transistor provided in a thin silicon layer (5) adjoining a surface (4) of a silicon body (3) and insulated from a silicon substrate (7) by a buried oxide layer (6). The channel region (13) of a first cond... | 06/11/2002 |
| 5945699 | Reduce width, differentially doped vertical JFET device A load device for an MOS transistor, such as that of a memory cell, includes a differentially doped vertical JFET structure that contains two separate and distinct opposite conductivity type regions. The interior region has the same conductivity as the we... | 08/31/1999 |
| 5824575 | Semiconductor device and method of manufacturing the same After forming an n-type active layer, an n+ -type source region and an n+ -type drain region at predetermined regions of a GaAs substrate, a silicon oxide film and a silicon nitride film are deposited, and then source and drain elect... | 10/20/1998 |
| 5789771 | Camel-gate field-effect transistor with multiple modulation-doped channels The invention relates to the structure of the camel-gate field-effect transistor with multiple modulation-doped channels. The device structure, from the bottom to the top in succession, includes the substrate, the buffer layer, the multiple modulation-dop... | 08/04/1998 |
| 5714777 | Si/SiGe vertical junction field effect transistor A junction field effect transistor and method for making is described incorporating horizontal semiconductor layers within an opening to form a channel and a semiconductor layer through which the opening was made which forms a gate electrode surrounding t... | 02/03/1998 |
| 5639688 | Method of making integrated circuit structure with narrow line widths In a sub-micron line width process, a first layer of polysilicon 13 is patterned into lines 1,2 spaced a predetermined distance. An oxide layer 11 is deposited. A second layer of polysilicon 14 is deposited on the insulating layer. A gate contact 19 or em... | 06/17/1997 |
| 5536953 | Wide bandgap semiconductor device including lightly doped active region A semiconductor device for providing stable operation over a relatively wide temperature range includes a wide bandgap semiconductor active region having an intentional dopant of a first conductivity type and an unintentional impurity of a second conducti... | 07/16/1996 |
| 5432377 | Dielectrically isolated semiconductor device and a method for its manufacture A semiconductor device is supported by a semiconductor body which comprises a substrate, an oxide layer and a weakly doped monocrystalline wafer. Trenches for a dielectrically isolating layer which surrounds a component region are etched in the wafer. A f... | 07/11/1995 |
| 5428234 | Semiconductor device A semiconductor device which comprises a semiconductor substrate having thereon a channel region, said channel region comprising (A) a channel, and (B) a metallic layer or a compound layer of a metal with a constituent material of the semiconductor substr... | 06/27/1995 |
| 5393998 | Semiconductor memory device containing junction field effect transistor The miniaturization of junction field effect transistors constituting memory cells and higher integration of a dynamic semiconductor memory device are attained. Word lines composed of a p-type impurity diffusion layer are formed on an n-type silicon subst... | 02/28/1995 |
| 5309007 | Junction field effect transistor with lateral gate voltage swing (GVS-JFET) A field effect transistor having a buried gate, and one or more gates disposed along the channel between the source and drain, which cooperate to cause the electric field within the channel along its length to be more uniform, and have a lower field maxim... | 05/03/1994 |
| 4959697 | Short channel junction field effect transistor A junction field effect transistor fabricated by a simplified process for incorporation into an integrated circuit including bipolar transistors is disclosed. The JFET comprises an isolated gate region of a first conductivity type with a surface on the in... | 09/25/1990 |
| 4698653 | Semiconductor devices controlled by depletion regions A field effect transistor is disclosed similar to a junction field effect transistor, but in which the depletion width in the channel due to a PN junction adjoining the channel is controlled not by directly controlling the reverse voltage on the PN juncti... | 10/06/1987 |
| 4670764 | Multi-channel power JFET with buried field shaping regions A power JFET (2) has a stack (4) of alternating conductivity type layers (5-9) forming a plurality of channels (6, 8). The JFET has an ON state conducting bidirectional current horizontally through the channels. The channels are stacked vertically, and th... | 06/02/1987 |
| 4635084 | Split row power JFET A power JFET (2) has a common drift region (4) between split first and second longitudinally separated sets of rows (6, 8) of alternating conductivity type layers (10-20 and 21-31) forming a plurality of channels (11, 13, 15, 17, 19, 22, 24, 26, 28 and 30... | 01/06/1987 |
| 4633281 | Dual stack power JFET with buried field shaping depletion regions A power JFET (2) has a common drift region (4) between a pair of spaced first and second stacks (6, 8) of alternating conductivity type layers (10-14 and 15-19) forming a plurality of channels (11, 13, 16 and 18). The JFET has an ON state conducting bidir... | 12/30/1986 |
| 4596068 | Process for minimizing boron depletion in N-channel FET at the silicon-silicon oxide interface The surface of the channel and top gates of N channel IGFETS and JFETS respectively are compensated after a high temperature processing by ion implanting boron through a protective layer. The peak impurity concentration is to occur in a sacrificial gate p... | 06/24/1986 |
| 4477963 | Method of fabrication of a low capacitance self-aligned semiconductor electrode structure Semiconductor electrode structure with low parasitic capacitance and method for forming low capacitance first and second electrodes in a semiconductor device, such as a static induction transistor, while avoiding the requirement for precision mask alignme... | 10/23/1984 |
| 4449284 | Method of manufacturing an integrated circuit device having vertical field effect transistors A method of manufacturing an integrated circuit device including vertical static induction transistors (SIT) having a first recess between the gate region and the drain (or source) region to reduce the capacitance between both regions and a second recess ... | 05/22/1984 |
| 4393575 | Process for manufacturing a JFET with an ion implanted stabilization layer A semiconductor device wherein surface stabilization is provided by a shallow layer of ion implanted doping material on the surface of the semiconductor and beneath the passivating oxide layer. One embodiment is a bipolar transistor including a collector ... | 07/19/1983 |
| 4306246 | Method for trimming active semiconductor devices A method for achieving active devices with closely matched characteristics for use in high performance monolithic integrated circuits. The method comprises providing active devices with appropriately segmented junction regions connected in parallel by the... | 12/15/1981 |
| 4262296 | Vertical field effect transistor with improved gate and channel structure A high frequency field effect transistor of gallium arsenide or other III-V semiconductor compounds has a preferentially etched trapezoidal groove structure in the top surface which creates parallel trapezoidal semiconductor fingers that are wider at the ... | 04/14/1981 |
| 4242692 | Charge transfer device which has a pair of straight portions joined by a direction changing portion The present invention relates to a charge transfer device which allows change of the charge transfer direction wherein transfer portions are formed of generally rectangular shape which have a length in the charge transfer direction which gradually gets lo... | 12/30/1980 |
| 4216490 | Static induction transistor A static induction transistor having a channel region between a gate region and a source region of the transistor. Current flowing from the drain region to the source region through the channel region is controlled by a voltage applied to the gate region.... | 08/05/1980 |
| 4209795 | Jsit-type field effect transistor with deep level channel doping A field effect transistor of the type wherein the conductivity of the channel thereof is variable by injecting the minority carriers into the channel from the gate thereof, is disclosed. The channel of the transistor includes minority carrier recombinatio... | 06/24/1980 |
| 4152714 | Semiconductor apparatus A field-effect transistor device is provided having a relatively substantial capability to withstand reverse bias voltages. The device can also be provided having a relatively low "on" condition resistance between the source and drain terminals thereof by... | 05/01/1979 |
| 4148047 | Semiconductor apparatus A field-effect transistor device is provided having a relatively low "on" condition resistance between the source and drain terminals thereof by virtue of the geometrical design used.... | 04/03/1979 |
| 4143386 | Junction type field effect transistor A junction type field effect transistor comprises a source region and a drain region extending into a semiconductor body further than the channel region and a gate region located entirely within the channel region between the source and drain regions, lea... | 03/06/1979 |
| 4049476 | Method of manufacturing a semiconductor integrated circuit device which includes at least one V-groove jfet and one bipolar transistor A method of manufacturing a semiconductor integrated circuit device, which includes at least one junction field-effect transistor and at least one bipolar transistor, is characterized in that a groove portion is formed by chemically etching a part of a di... | 09/20/1977 |