Class 257/E29.056 - With variation of composition of channel (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E29.051. This
No. of patents: 80
Last issue date: 05/01/2007

«First «Previous1 2 Next»Last»

Number	Title	Issue Date
7211869	Increasing carrier mobility in NFET and PFET transistors on a common wafer Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partial...	05/01/2007
6703648	Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed to the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow s...	03/09/2004
6703688	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p...	03/09/2004
6703271	Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The compos...	03/09/2004
6699764	Method for amorphization re-crystallization of Si1-xGex films on silicon substrates A method of fabricating a Si1-X GeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1-X GeX layer on the silicon substrate forming a Si1-X GeX...	03/02/2004
6690043	Semiconductor device and method of manufacturing the same A semiconductor device comprises a base substrate, an insulating film formed on the substrate, an undoped first and lattice-relaxed semiconductor layer formed on the insulating film, a second semiconductor layer having a tensile strain and formed on the f...	02/10/2004
6677192	Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p...	01/13/2004
6657223	Strained silicon MOSFET having silicon source/drain regions and method for its fabrication A strained silicon MOSFET utilizes a strained silicon layer formed on a silicon germanium layer. Strained silicon and silicon germanium are removed at opposing sides of the gate and are replaced by silicon regions. Deep source and drain regions are implan...	12/02/2003
6645836	Method of forming a semiconductor wafer having a crystalline layer thereon containing silicon, germanium and carbon A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly ha...	11/11/2003
6646322	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p...	11/11/2003
6642106	Method for increasing core gain in flash memory device using strained silicon A method of memory device fabrication. In one embodiment, the method of memory device (400) fabrication comprises implanting an element (200) in a substrate (440). The element (200) causes an inherent elongational realignment of atoms in silicon (101,102)...	11/04/2003
6635909	Strained fin FETs structure and method A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side o...	10/21/2003
6633066	CMOS integrated circuit devices and substrates having unstrained silicon active layers CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si	10/14/2003
6630710	Elevated channel MOSFET The present invention provides a semiconductor device (e.g., MOSFET) having a channel above the surface of the wafer containing a well and a junction. The elevated channel may be selectively epitaxially grown and enables higher mobility, thereby enabling ...	10/07/2003
6627515	Method of fabricating a non-floating body device with enhanced performance A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semicondu...	09/30/2003
6627522	Method for enhancing the solubility of dopants in silicon A method for enhancing the equilibrium solid solubility of dopants in silicon, germanium and silicon-germanium alloys. The method involves subjecting silicon-based substrate to biaxial or compression strain. It has been determined that boron solubility wa...	09/30/2003
6621131	Semiconductor transistor having a stressed channel A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and...	09/16/2003
6617228	Semiconductor material and method for enhancing solubility of a dopant therein A method for enhancing the equilibrium solubility of boron and indium in silicon. The method involves first-principles quantum mechanical calculations to determine the temperature dependence of the equilibrium solubility of two important p-type dopants in...	09/09/2003
6597016	Semiconductor device and method for fabricating the same An Si1-y Gey layer (where 0	07/22/2003
6593641	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p...	07/15/2003
6593191	Buried channel strained silicon FET using a supply layer created through ion implantation A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supp...	07/15/2003
6566734	Semiconductor device In making a field effect transistor, a dummy gate electrode is formed before a gate electrode is formed. Extension regions, a side wall silicon nitride film, source/drain regions, a silicon oxide film, and other elements are formed with respect to the dum...	05/20/2003
6563152	Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel A method for forming a strain layer on an underside of a channel in an MOS transistor in order to produce a mechanical stress in the channel, increasing a mobility of carriers in the channel and an apparatus produced from such a method....	05/13/2003
6555839	Buried channel strained silicon FET using a supply layer created through ion implantation A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or burie...	04/29/2003
6544854	Silicon germanium CMOS channel A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon germanium channel layer on the substrate. A gate insulation layer is formed on top of the strained silicon germanium channel layer, ...	04/08/2003
6525338	Semiconductor substrate, field effect transistor, method of forming SiGe layer and method of forming strained Si layer using same, and method of manufacturing field effect transistor A semiconductor substrate, a field effect transistor, a method of forming a SiGe layer and a method of forming a strained Si layer using the same, and a method of manufacturing a field effect transistor are provided, which enable the threading dislocation...	02/25/2003
6518134	Method for fabricating a semiconductor device with an air tunnel formed in the lower part of a transistor channel A method for fabricating a semiconductor device, which improves the threshold voltage by forming an air tunnel in the lower part of the transistor channel of a semiconductor device, and also improves the short channel effect by making better the sub-thres...	02/11/2003
6507091	Transistor with indium-implanted SiGe alloy and processes for fabricating the same An indium-implanted transistor is provided. The transistor has a silicon channel region that includes a buried layer of an Si1-x Gex alloy into which indium is implanted, with 10-5ࣘxࣘ4×10.sup.-1. A first method for ...	01/14/2003
6492216	Method of forming a transistor with a strained channel A method of forming a tensile or compressive strained channel region for a semiconductor device, such as a MOSFET device, allowing improved carrier transport properties and increased device performance to be realized, has been developed. The method featur...	12/10/2002
6486510	Reduction of reverse short channel effects by implantation of neutral dopants A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and dr...	11/26/2002
6486520	Structure and method for a large-permittivity gate using a germanium layer A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a...	11/26/2002
6476412	Light emitting semiconductor device with partial reflection quantum-wave interference layers A semiconductor device is constituted by a quantum-wave interference layer with plural periods of a pair of a first layer W and a second layer B. The second layer B has wider band gap than the first layer W. Each thickness of the first layer W and the sec...	11/05/2002
6472685	Semiconductor device A first silicon layer (Si layer), a second silicon layer (Si1 Cy layer) containing carbon and a third silicon layer not containing carbon are stacked in this order on a silicon substrate. Since the lattice constant of the Si1-y	10/29/2002
6461945	Solid phase epitaxy process for manufacturing transistors having silicon/germanium channel regions A method of manufacturing an integrated circuit utilizes solid phase epitaxy to form a channel region. The method includes providing an amorphous semiconductor material including germanium, crystallizing the amorphous semiconductor material via solid phas...	10/08/2002
6429061	Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation A strained Si CMOS structure is formed by steps which include forming a relaxed SiGe layer on a surface of a substrate; forming isolation regions and well implant regions in said relaxed SiGe layer; and forming a strained Si layer on said relaxed SiGe lay...	08/06/2002
6410371	Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer A method of forming a semiconductor-on-insulator (SOI) wafer. The method includes the steps of providing a first wafer, the first wafer having a silicon substrate and an oxide layer disposed thereon; providing a second wafer, the second wafer having a sil...	06/25/2002
6406973	Transistor in a semiconductor device and method of manufacturing the same The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P+ salicide forming technology having an elevated channel and a source/drain using the selective ...	06/18/2002
6403976	Semiconductor crystal, fabrication method thereof, and semiconductor device A Si1-x Gex /Si1-y Cy short-period superlattice which functions as a single SiGeC layer is formed by alternately growing Si1-x Gex layers (0	06/11/2002
6352912	Reduction of reverse short channel effects by deep implantation of neutral dopants A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and dr...	03/05/2002
6350993	High speed composite p-channel Si/SiGe heterostructure for field effect devices A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second com...	02/26/2002

«First «Previous1 2 Next»Last»

PatentStorm

Famous Patents

PatentStorm News

Class 257/E29.056 - With variation of composition of channel (EPO)