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| Number | Title | Issue Date |
| 6690060 | Field effect transistor and method of fabricating the same by controlling distribution condition of impurity region with implantation of additional ion A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide ... | 02/10/2004 |
| 6673663 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 01/06/2004 |
| 6653686 | Structure and method of controlling short-channel effect of very short channel MOSFET A semiconductor device comprising a gate having an approximately 0.05 μm channel length, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the ... | 11/25/2003 |
| 6642599 | Semiconductor device and method of manufacturing the same A high resistance n-type base layer is formed on a silicon substrate with an insulating layer made of a silicon oxide film therebetween. In the high resistance n-type base layer a p-ch MOS transistor is formed. The p-ch MOS transistor is electrically isol... | 11/04/2003 |
| 6638801 | Semiconductor device and its manufacturing method A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than... | 10/28/2003 |
| 6624455 | Semiconductor device and method of manufacturing the same including drain pinned along channel width In a semiconductor device, pining regions 105 are disposed along the junction portion of a drain region 102 and a channel forming region 106 locally in a channel width direction. With this structure, because the spread of a depletion layer from a drain si... | 09/23/2003 |
| 6610573 | Method for forming a single wiring level for transistors with planar and vertical gates on the same substrate A memory cell comprises a region containing one or more vertical pass transistor, and a support region containing, e.g. one or more planar transistors. During processing, a polysilicon layer is formed for the planar devices gate. The polysilicon layer is ... | 08/26/2003 |
| 6599804 | Fabrication of field-effect transistor for alleviating short-channel effects Short-channel threshold voltage roll-off and punchthrough in an IGFET (40 or 42) having a channel zone (64 or 84) situated in body material (50) are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a loc... | 07/29/2003 |
| 6576966 | Field-effect transistor having multi-part channel An asymmetric insulated-gate field-effect transistor (40) is configured in an asymmetric lightly doped drain structure that alleviates hot-carrier effects and enables the source characteristics to be decoupled from the drain characteristics. The transisto... | 06/10/2003 |
| 6566734 | Semiconductor device In making a field effect transistor, a dummy gate electrode is formed before a gate electrode is formed. Extension regions, a side wall silicon nitride film, source/drain regions, a silicon oxide film, and other elements are formed with respect to the dum... | 05/20/2003 |
| 6562687 | MIS transistor and method for making same on a semiconductor substrate The invention relates to an MIS transistor comprising a channel region (118), source (114) and drain (116) regions arranged on either side of the channel, and a gate (150) set closely above the channel region. According to the invention, the channel has a... | 05/13/2003 |
| 6548842 | Field-effect transistor for alleviating short-channel effects An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local su... | 04/15/2003 |
| 6544851 | Method of manufacturing a semiconductor device having a pocket implant in channel region In a method of manufacturing a semiconductor device comprising a semiconductor body (1) of a first conductivity type which is provided at a surface (2) with a transistor having a gate (28) insulated from a channel (13) provided at the surface (2) of the s... | 04/08/2003 |
| 6531379 | High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the pr... | 03/11/2003 |
| 6509241 | Process for fabricating an MOS device having highly-localized halo regions A process for fabricating an MOS device having a highly-localized halo region includes the formation of a first halo region at a first surface of a silicon substrate, and a second halo region at a second surface of the silicon substrate. The second surfac... | 01/21/2003 |
| 6503805 | Channel implant through gate polysilicon A field effect transistor having a doped region in the substrate immediately underneath the gate of the transistor and interposed between the source and drain of the transistor is provided. The doped region has a retrograde dopant profile such that the do... | 01/07/2003 |
| 6498376 | Semiconductor device and manufacturing method thereof A MISFET is provided with a segmented channel comprising regions in which the channel is inverted by a first gate voltage and regions in which the channel is inverted by a second gate voltage. The MISFET is formed in a semiconductor substrate having a fir... | 12/24/2002 |
| 6492232 | Method of manufacturing vertical semiconductor device An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently change... | 12/10/2002 |
| 6486014 | Semiconductor device and method of manufacturing the same In a semiconductor device, pining regions 105 are disposed along the junction portion of a drain region 102 and a channel forming region 106 locally in a channel width direction. With this structure, because the spread of a depletion layer from a drain si... | 11/26/2002 |
| 6482691 | Seismic imaging using omni-azimuth seismic energy sources and directional sensing Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 11/19/2002 |
| 6479846 | Metal oxide semiconductor field effect transistor having a relatively high doped region in the channel for improved linearity A field effect transistor is disclosed having a relatively high doped region (of the same type dopant as the channel) to reduce the change in the depletion region within the channel with changes in the drain voltage (Vd). Changes in the drain current (Id)... | 11/12/2002 |
| 6479356 | Method of manufacturing a semiconductive device with an enhanced junction breakdown strength A gate insulating film and gate electrodes are formed on a substrate containing N-type impurities such as P or As. Under the gate insulating film is a gate region on both sides of which are a first and a second source drain region. The gate region is furn... | 11/12/2002 |
| 6475852 | Method of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 11/05/2002 |
| 6472260 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 10/29/2002 |
| 6448120 | Totally self-aligned transistor with tungsten gate A totally self-aligned transistor with a tungsten gate. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. A mid-gap electrode is also self-aligned to... | 09/10/2002 |
| 6413823 | Methods of forming field effect transistors Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 07/02/2002 |
| 6406957 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 06/18/2002 |
| 6403426 | Method of manufacturing a semiconductor device In a method of manufacturing a semiconductor device comprising a transistor having a gate insulated from a channel region at a surface of a semiconductor body by a gate dielectric, an active region 4 of a first conductivity type is defined at the surface ... | 06/11/2002 |
| 6400002 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 06/04/2002 |
| 6396103 | Optimized single side pocket implant location for a field effect transistor A field effect transistor (300) having a source region (304) and a drain region (306) includes a source side halo region (332) formed at a junction between the source region and a channel region to substantially interrupt off state leakage current. The so... | 05/28/2002 |
| 6380041 | Semiconductor with laterally non-uniform channel doping profile and manufacturing method therefor An ultra-large scale integrated circuit semiconductor device having a laterally non-uniform channel doping profile is manufactured by using a Group IV element implant at an implant angle of between 0° to 60° from the vertical to create interstitials in ... | 04/30/2002 |
| 6373102 | Process for fabricating a channel region of a transistor device with ion implantation and the transistor device formed therefrom The invention is related to a method for fabricating a channel region of a transistor device by ion implantation with a large angle and the transistor device formed therefrom. The transistor device is formed on a substrate. Furthermore, the ion implantati... | 04/16/2002 |
| 6355963 | MOS type semiconductor device having an impurity diffusion layer A semiconductor device of the invention is formed so that the impurity concentration of a semiconductor substrate (1) under a source diffusion layer (2) is lower than the impurity concentration on a source side of a p-type impurity diffusion layer (6). Th... | 03/12/2002 |
| 6344382 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 02/05/2002 |
| 6337249 | Semiconductor device and fabrication process thereof A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type t... | 01/08/2002 |
| 6335234 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 01/01/2002 |
| 6335246 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 01/01/2002 |
| 6316809 | Analog MOSFET devices The specification describes MOS transistors for analog functions which have increased output impedance. The increased output impedance is the result of reduced drain depletion width. This is accomplished without adverse effects on other device parameters.... | 11/13/2001 |
| 6306709 | Semiconductor device and manufacturing method thereof In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. Th... | 10/23/2001 |
| 6297533 | LDMOS structure with via grounded source A lateral conduction MOS structure characterized by reduced source resistance and reduced pitch. The structure includes a semiconductor substrate having an epitaxial semiconductor layer thereon, the substrate and epitaxial layer being of the same conducti... | 10/02/2001 |
