Class 257/E29.051 - With insulated gate (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E29.05. This subclass
No. of patents: 159
Last issue date: 03/13/2007

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Number	Title	Issue Date
6677210	High voltage transistors with graded extension High voltage transistors with high breakdown voltages are provided. These high voltage transistors are formed with graded drain extension regions. The concentration of charge carriers increases farther away from the gate across each drain extension region...	01/13/2004
6624451	High frequency field effect transistor with carrier extraction to reduce intrinsic conduction A field effect transistor (FET) is of the type which employs base biasing to depress the intrinsic contribution to conduction and reduce leakage current. It incorporates four successive layers (102 to 108): a p+ InSb base layer (102), a p+...	09/23/2003
6617647	Insulated gate semiconductor device and method of manufacturing the same Dot-pattern-like impurity regions 104 are artificially and locally formed on a channel forming region 103. The impurity regions 104 restrain the expansion of a drain side depletion layer toward the channel forming region 103 to prevent the short channel e...	09/09/2003
6602745	Field effect transistor and method of fabrication An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge ...	08/05/2003
6603143	Semiconductor device and method for fabricating same A semiconductor device includes a semiconductor substrate having a trench in its surface, an insulating film in the trench, a doped conductive layer on the insulating film, a gate insulation film and a gate electrode on the doped conductive layer over the...	08/05/2003
6597026	Semiconductor device comprising plural isolated channels in a shallow trench isolation region A semiconductor device includes a plurality of shallow trench isolation bands, a plurality of channels, a source electrode, a drain electrode, and a gate electrode. The shallow trench isolation bands are formed in a band-like shape within an element forma...	07/22/2003
6593174	Field effect transistor having dielectrically isolated sources and drains and method for making same A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semicond...	07/15/2003
6579768	Field effect transistor and method of fabrication An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge ...	06/17/2003
6566695	Hyperbolic type channel MOSFET In a MOSFET, a source region, a drain region and a channel region disposed between the source region and the drain region are provided. And the width W(x) of the channel region is changed according to the following mathematical equation. ##EQU1## In ...	05/20/2003
6548866	Field effect transistor with reduced narrow channel effect In a field effect transistor, an element isolation trench is formed around the element region on the major surface of a silicon substrate. A gate electrode is formed on the major surface in the element region via a gate insulating film. Source and drain r...	04/15/2003
6541825	Semiconductor device including impurity layer having continuous portions formed at different depths and method of manufacturing the same A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltag...	04/01/2003
6541804	Junction-isolated lateral MOSFET for high-/low-side switches The junction insulated lateral MOSFET is suitable for high/low side switches. A p-conductive wall between an n-conductive source zone and an n-conductive drain zone, together with the source zone and drain zone, extend to an n-conductive substrate. The so...	04/01/2003
6537888	Method for fabricating a semiconductor device reducing junction leakage current and narrow width effect A semiconductor device for reducing junction leakage current and mitigating the narrow width effect, and a fabrication method thereof, are provided. The semiconductor device includes a semiconductor substrate in which an active region and an isolation reg...	03/25/2003
6534369	Field effect transistor and method of fabrication An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge ...	03/18/2003
6525376	High withstand voltage insulated gate N-channel field effect transistor A high withstand voltage insulated gate N-channel field effect transistor has a P-type semiconductor substrate and an N-type epitaxial layer formed on the semiconductor substrate. An N-type source region having a high concentration is formed on the epitax...	02/25/2003
6472277	Method for fabricating a semiconductor device with an improved short channel effect A semiconductor device includes a semiconductor substrate having a trench in its surface, an insulating film in the trench, a doped conductive layer on the insulating film, a gate insulation film and a gate electrode on the doped conductive layer over the...	10/29/2002
6445034	MOS transistor having first and second channel segments with different widths and lengths In order to enable non-integer current ratios to be produced in current mirror circuits using small transistors the channel area is adjusted by changes in the channel length over part of the width of the channel. In further embodiments the transistor is f...	09/03/2002
6420764	Field effect transitor having dielectrically isolated sources and drains and methods for making same A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semicond...	07/16/2002
6404022	AM/PM non-linearities in FETs When a field effect transistor (e.g., an LDMOSFET) saturates, the electrons traveling through the device slow down. This causes a phase shift with respect to electrons that travel through the device when the device is not saturated. By providing a shorter...	06/11/2002
6387766	Method for manufacturing an integrated circuit with low threshold voltage differences of the transistors therein In an integrated circuit with low threshold voltage differences of the transistors and a manufacturing process for such an integrated circuit, MOS transistors of different lengths but having threshold voltages that are substantially the same are made by a...	05/14/2002
6384455	MOS semiconductor device with shallow trench isolation structure and manufacturing method thereof A MOS IC device and a manufacturing method thereof capable of readily improving the isolation breakdown voltage while achieving a low threshold value and low junction capacitance with sufficient well-region separation breakdown voltage. To this end, a bur...	05/07/2002
6380036	Semiconductor device and method of manufacturing the same A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate...	04/30/2002
6365947	Semiconductor device and method of increasing channel length to eliminate short channel effects of corner devices A method of increasing the channel length for small semiconductor devices having decreased gate dimensions, thus reducing or eliminating short channel effects for corner devices. The method generally includes forming a gate electrode and defining first an...	04/02/2002
6300221	Method of fabricating nanoscale structures A method includes forming a spacer mask having a defined edge over a portion of a substrate, and alternatively conformally depositing over a portion of a substrate including the spacer mask a predetermined member of at least a first material and a second ...	10/09/2001
6274915	Method of improving MOS device performance by controlling degree of depletion in the gate electrode A design for an MOS transistor deliberately uses depletion in a polysilicon gate electrode to improve circuit performance. Conventional transistor design seeks to minimize depletion in a polysilicon gate electrode to increase drive current. According to a...	08/14/2001
6271093	Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETs Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sen...	08/07/2001
6268629	Field effect transistor with reduced narrow channel effect In a field effect transistor, an element isolation trench is formed around the element region on the major surface of a silicon substrate. A gate electrode is formed on the major surface in the element region via a gate insulating film. Source and drain r...	07/31/2001
6229188	MOS field effect transistor and its manufacturing method The present invention provides novel structures of MOS field effect transistor which operate with high speed and low power consumption. This has been achieved through providing epitaxial growth layers on a substrate of high impurity doping concentration i...	05/08/2001
6225151	Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing...	05/01/2001
6221707	Method for fabricating a transistor having a variable threshold voltage A method for fabricating a transistor having a variable threshold voltage is disclosed. Energy levels of a transistor can be represented by a valance band, a conduction band, and a Fermi level. In order to fabricate a transistor with a variable threshold ...	04/24/2001
6221703	Method of ion implantation for adjusting the threshold voltage of MOS transistors The invention relates to an ion implantation method for adjusting the threshold voltage of MOS transistors. The MOS transistor is employed in a DRAM (dynamic random access memory) memory cell in a semiconductor wafer and comprises a substrate, a gate insu...	04/24/2001
6218714	Insulated gate semiconductor device and method of manufacturing the same Dot-pattern-like impurity regions 104 are artificially and locally formed on a channel forming region 103. The impurity regions 104 restrain the expansion of a drain side depletion layer toward the channel forming region 103 to prevent the short channel e...	04/17/2001
6208950	Noise reduction method for a semiconductor device A 1/f noise coefficient characteristic with respect to an operating point of a semiconductor device is measured, and a control voltage corresponding to an operating point of the semiconductor device with which the 1/f noise coefficient is minimized is app...	03/27/2001
6198141	Insulated gate semiconductor device and method of manufacturing the same Dot-pattern-like impurity regions are artificially and locally formed in a channel forming region. The impurity regions restrain the expansion of a drain side depletion layer toward the channel forming region to prevent the short channel effect. The impur...	03/06/2001
6177322	High voltage transistor with high gated diode breakdown voltage A high voltage transistor exhibiting high gated diode breakdown voltage is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the...	01/23/2001
6177299	Transistor having substantially isolated body and method of making the same A method for forming a field effect transistor (FET) is disclosed which includes forming an isolation region in a substrate of semiconductor material, anisotropically etching the substrate such that a sidewall spacer region of semiconductor material remai...	01/23/2001
6153910	Semiconductor device with nitrogen implanted channel region A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate...	11/28/2000
6153907	IC layout structure for MOSFET having narrow and short channel A specific IC layout structure for the MOSFET having a narrow and short channel, especially when the width and the length of the channel are both as small as 1 micron or less, is disclosed. In the IC layout structure, a mask includes a first mask region f...	11/28/2000
6121115	Methods of fabricating integrated circuit memory devices having wide and narrow channel stop layers An integrated circuit memory device includes a semiconductor substrate having a memory cell area and a select transistor area. A first field insulation layer is included in the memory cell area, and a first channel stop impurity layer is included beneath ...	09/19/2000
6117721	Semiconductor processing method of forming a static random access memory cell and static random access memory cell A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area region...	09/12/2000

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Class 257/E29.051 - With insulated gate (EPO)