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| Number | Title | Issue Date |
| 7439593 | Semiconductor device having silicide formed with blocking insulation layer Some embodiments include an isolation layer defining an active region of a substrate, a gate pattern formed on the active region, and source/drain regions formed in the active region. Sidewall spacers are formed on sidewalls of the gate pattern, and a blocking insul... | 10/21/2008 |
| 7385237 | Fin field effect transistors with low resistance contact structures Fin FET semiconductor devices are provided which include a substrate, an active pattern that protrudes vertically from the substrate and that extends laterally in a first direction, a device isolation layer which has a top surface that is lower than a top surface of... | 06/10/2008 |
| 7358567 | High-voltage MOS device and fabrication thereof A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying d... | 04/15/2008 |
| 7355253 | Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric fo... | 04/08/2008 |
| 7307314 | LDMOS transistor with improved gate shield A LDMOS transistor having a gate shield provides reduced drain coupling to the gate shield and source by restricting the thickness of the gate shield and by confining a source contact to the source region without overlap of the gate. ... | 12/11/2007 |
| 7304347 | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial l... | 12/04/2007 |
| 7253472 | Method of fabricating semiconductor device employing selectivity poly deposition A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gat... | 08/07/2007 |
| 7122831 | Method of forming a reflective electrode and a liquid crystal display device The present invention provides a method of forming a TFT and a reflective electrode having recesses or projections with reduced manufacturing cost and a reduced number of manufacturing steps, and provides a liquid crystal display device to which the method is applie... | 10/17/2006 |
| 6703665 | Transistor A withstand voltage region of a second conductivity type is formed in a drain layer of a first conductivity type in a semiconductor substrate, and a conductive region of the first conductivity type is partly formed in the withstand voltage region by being... | 03/09/2004 |
| 6699740 | Method for manufacturing a lateral double-diffused MOS transistor having stable characteristics and equal drift length A semiconductor device including a P-type semiconductor layer; an N-type first well on the surface of the semiconductor layer; a P-type second well on the surface of the first well; an N-type source region on the surface of the second well; and an N-type ... | 03/02/2004 |
| 6700156 | Insulated gate semiconductor device An insulated gate semiconductor device includes a first semiconductor layer of a first conductivity type. A plurality of second semiconductor layers of a second conductivity type selectively formed in a surface area of the first semiconductor layer. At le... | 03/02/2004 |
| 6700160 | Double-diffused MOS (DMOS) power transistor with a channel compensating implant An improved DMOS power transistor (20) with a single p-body implant (12) and including an n-type channel compensating implant (NCCI) (24). The improved DMOS power transistor (20) provides a more favorable trade-off between threshold voltage (VT... | 03/02/2004 |
| 6696726 | Vertical MOSFET with ultra-low resistance and low gate charge A vertical trench double-diffused metal-oxide-semiconductor (DMOS) field effect transistor characterized by a reduced drain-to-source resistance and a lower gate charge and providing a high transconductance and an enhanced frequency response.... | 02/24/2004 |
| 6693339 | Semiconductor component and method of manufacturing same A semiconductor component includes a first semiconductor region (110, 210) having a first conductivity type and a second semiconductor region (120, 220) above the first semiconductor region and having a second conductivity type. The semiconductor componen... | 02/17/2004 |
| 6693024 | Semiconductor component with a semiconductor body having a multiplicity of pores and method for fabricating The semiconductor component is fabricated on the basis of a semiconductor body with a first and a second surface. A multiplicity of pores are formed in the semiconductor body. The pores extend into the semiconductor body proceeding from the first surface ... | 02/17/2004 |
| 6693338 | Power semiconductor device having RESURF layer A semiconductor device includes a drain layer, first and second drift layers, a RESURF layer, a drain electrode, a base layer, a source layer, a source electrode, and a gate electrode. The first drift layer is formed on the drain layer. The second drift l... | 02/17/2004 |
| 6686626 | Source-down power transistor The invention relates to a source-down power transistor, in which narrow trenches filled with insulated polysilicon are provided between a source pillar and a drain pillar. Inversion channels form on the side walls of the trenches when a positive drain vo... | 02/03/2004 |
| 6683349 | Semiconductor device and method of manufacturing the same A semiconductor device includes a gate electrode 16 on a P type well through a gate oxide film 9, a heavily-doped N+ type source layer 12 formed to be adjacent to the one end of the gate electrode 16, an N+ type drain layer 12 formed apart from the other ... | 01/27/2004 |
| 6677642 | Field effect transistor structure and method of manufacture A field effect transistor structure is formed with a body semiconductor layer (5) having source (9), body (7), drift region and drain (11). An upper semiconductor layer (21) is separated from the body by an oxide layer (17). The upper semiconductor layer ... | 01/13/2004 |
| 6677641 | Semiconductor structure with improved smaller forward voltage loss and higher blocking capability A semiconductor device is disclosed. The semiconductor device includes one or more charge control electrodes a plurality of charge control electrodes. The one or more charge control electrodes may control the electric field within the drift region of a se... | 01/13/2004 |
| 6677210 | High voltage transistors with graded extension High voltage transistors with high breakdown voltages are provided. These high voltage transistors are formed with graded drain extension regions. The concentration of charge carriers increases farther away from the gate across each drain extension region... | 01/13/2004 |
| 6664590 | Circuit configuration for load-relieved switching A circuit configuration for load-relieved switching has a bridge circuit with at least two controllable power switches, whose controlled paths are arranged in series with one another and between a first and a second supply potential. The circuit configura... | 12/16/2003 |
| 6664593 | Field effect transistor structure and method of manufacture A field effect transistor structure is formed with a body semiconductor layer (1) having source (3), channel (7), drift region (9) and drain (5). An upper metallisation layer (15, 17) is separated from the body by an oxide layer (11). The upper metallisat... | 12/16/2003 |
| 6664594 | Power MOS device with asymmetrical channel structure for enhanced linear operation capability A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the devi... | 12/16/2003 |
| 6664596 | Stacked LDD high frequency LDMOSFET A novel silicon RF LDMOSFET structure based on the use of a stacked LDD, is disclosed. The LDD has been modified from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. T... | 12/16/2003 |
| 6661056 | DMOS transistor protected against polarity reversal The present invention relates to a circuit configuration for protecting against polarity reversal of a DMOS transistor. A charge carrier zone (30) is provided, situated in the drift zone (14) of DMOS transistor (10), made up of individual partial charge carrie... | 12/09/2003 |
| 6657254 | Trench MOSFET device with improved on-resistance A trench MOSFET device and method of making the same. The trench MOSFET device comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower major... | 12/02/2003 |
| 6649974 | Field-effect controlled semiconductor device having a non-overlapping gate electrode and drift region and its manufacturing method A semiconductor component includes a first connection zone of a first conductivity type for providing a contact at a first side of a semiconductor body and a second connection zone of the first conductivity type for providing a contact at the second side ... | 11/18/2003 |
| 6639277 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 10/28/2003 |
| 6635926 | Field effect transistor with high withstand voltage and low resistance A field effect transistor with a high withstand voltage and a low resistance is provided. A ring-shaped channel region is disposed inside a source region formed in a ring, and the inside of the channel region is taken as a drain region. A depletion layer ... | 10/21/2003 |
| 6633065 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 10/14/2003 |
| 6624469 | Vertical MOS transistor having body region formed by inclined ion implantation There is provided a vertical MOS transistor in which a high frequency characteristic is improved, a low voltage operation is realized, and a stable characteristic with less fluctuation is obtained. After trench gate oxidation, a body is formed at a side w... | 09/23/2003 |
| 6620653 | Semiconductor device and method of manufacturing the same A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is ... | 09/16/2003 |
| 6621121 | Vertical MOSFETs having trench-based gate electrodes within deeper trench-based source electrodes Vertical MOSFETs include a semiconductor substrate having a plurality of semiconductor mesas therein that are separated by a plurality of deep stripe-shaped trenches. These stripe-shaped trenches extend in parallel and lengthwise across the substrate in a... | 09/16/2003 |
| 6617652 | High breakdown voltage semiconductor device A high breakdown voltage semiconductor device includes a semiconductor layer, a drain offset diffusion region, a source diffusion region, a drain diffusion region, a buried diffusion region of a first conductivity type that is buried in the drain offset d... | 09/09/2003 |
| 6613633 | Method for manufacturing a high power semiconductor device having a field plate extendedly disposed on a gate A method to fabricate a high voltage transistor of a smart power device is discussed. The method includes forming a well of first conductivity in a substrate of second conductivity; forming a drift layer of the second conductivity in the well; forming a s... | 09/02/2003 |
| 6613622 | Method of forming a semiconductor device and structure therefor A semiconductor device (10, 40) is formed to have a well (19) in a substrate (11). The well and the substrate have the same doping type, for example both P-type or both N-type. Low resistance contact regions (26, 27) of a second conductivity type are form... | 09/02/2003 |
| 6611021 | Semiconductor device and the method of manufacturing the same A semiconductor device includes an improved drain drift layer structure of alternating conductivity types, that is easy to manufacture, and that facilitates realizing a high current capacity and a high breakdown voltage and to provide a method of manufact... | 08/26/2003 |
| 6600188 | EEPROM with a neutralized doping at tunnel window edge An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. P-type lightly-doped drain regions are located at the polysilicon edges of the tunnel window. During the p... | 07/29/2003 |
| 6570219 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 05/27/2003 |
