Bizarre Patents
A gun that fires a missile, powered by gas "discharged by the operator of the toy."
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7420228 | Bipolar transistor comprising carbon-doped semiconductor A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a s... | 09/02/2008 |
| 7371650 | Method for producing a transistor structure A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and... | 05/13/2008 |
| 7323390 | Semiconductor device and method for production thereof The semiconductor device according to the invention includes a substrate, a field insulating region which delimits an active region of the semiconductor substrate, a collector, at least one collector contact region associated with the collector, and a base with an a... | 01/29/2008 |
| 6703686 | Semiconductor device An n-type low impurity concentration semiconductor layer is provided, by epitaxial growth or the like, on a p-type semiconductor substrate. In order to vertically form a semiconductor device in the low impurity concentration semiconductor layer, at least ... | 03/09/2004 |
| 6703685 | Super self-aligned collector device for mono-and hetero bipolar junction transistors The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is dispo... | 03/09/2004 |
| 6680497 | Interstitial diffusion barrier A heterojunction bipolar transistor is doped in the sub-collector layer (20) with phosphorus (24). The presence of the phosphorus causes any interstitial gallium (22) to be bonded (26) to the phosphorus (24) and move to a lattice site. The result is that ... | 01/20/2004 |
| 6674103 | HBT with nitrogen-containing current blocking base collector interface and method for current blocking An improved HBT of the invention reduces the current blocking effect at the base-collector interface. Nitrogen is incorporated at the base-collector interface in an amount sufficient to reduce the conduction band energy of the collector at the base-collec... | 01/06/2004 |
| 6664609 | High frequency differential amplification circuit with reduced parasitic capacitance Disclosed is a circuit layout of a differential amplification circuit that constitutes a Gilbert cell, in which two multiple finger bipolar transistors forming a differential amplifier are positioned substantially axially symmetrical to each other. The lo... | 12/16/2003 |
| 6649983 | Vertical bipolar transistor formed using CMOS processes A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a p-well region, a pocket base region and an emitter... | 11/18/2003 |
| 6627972 | Vertical bipolar transistor The invention relates to a vertical bipolar transistor and a method for the production thereof. The aim of the invention is to produce a vertical bipolar transistor and to disclose a method for the production thereof, whereby excellent high frequency prop... | 09/30/2003 |
| 6624497 | Semiconductor device with a reduced mask count buried layer An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of dif... | 09/23/2003 |
| 6590273 | Semiconductor integrated circuit device and manufacturing method thereof In the semiconductor integrated circuit device, a first P+ type buried layer formed as an anode region and an N+ type diffused region formed in a cathode region are spaced from each other in the direction of the depth. This makes it ... | 07/08/2003 |
| 6579773 | Transistor device and fabrication method thereof In the fabrication of a transistor device, particularly a low-voltage high-frequency transistor for use in mobile telecommunications, a method for improving the transistor performance and the high-frequency characteristics of the device is described. The ... | 06/17/2003 |
| 6569730 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 05/27/2003 |
| 6570242 | Bipolar transistor with high breakdown voltage collector A transistor that includes a doped buried region 320 within a semiconductor body 300, 340. The doped buried region includes a portion having a first thickness 348 and a second thickness, the first thickness being less than the second thickness. In one emb... | 05/27/2003 |
| 6563145 | Methods and apparatus for a composite collector double heterojunction bipolar transistor A compound collector double heterojunction bipolar transistor (CCHBT) incorporates a collector comprising two layers: a wide bandgap collector region (e.g., GaAs), and a narrow bandgap collector region (e.g., InGaP). The higher electric field is supported... | 05/13/2003 |
| 6559517 | Structure for a semiconductor device An exemplary embodiment of the invention is a semiconductor device comprising a substrate of a first conductivity type and a subcollector of a second conductivity type provided on the substrate. An intrinsic epitaxial layer is formed on the substrate. A c... | 05/06/2003 |
| 6555894 | Device with patterned wells and method for forming same In a semiconductor substrate having a top surface and a PN junction between a first region of one conductivity type formed by masked diffusion into a semiconductor from the surface and a second region of opposite conductivity type formed into a first port... | 04/29/2003 |
| 6538294 | Trenched semiconductor device with high breakdown voltage An arrangement in a semiconductor component includes a highly doped layer on a substrate layer and is delimited by at least one trench extending from the surface of the component through the highly doped layer. A sub-layer between the substrate layer and ... | 03/25/2003 |
| 6534802 | Method for reducing base to collector capacitance and related structure According to a disclosed embodiment, a transistor region comprising a collector region is opened adjacent to an oxide region. The oxide region may be, for example, a field oxide region. Additionally, an extrinsic collector region is formed under the oxide... | 03/18/2003 |
| 6518111 | Method for manufacturing and structure of semiconductor device with dielectric diffusion source and CMOS integration A method for manufacturing a semiconductor device includes forming a collector region of a semiconductor substrate and forming an isolation structure adjacent at least a portion of the collector region. The method also includes forming a gate stack layer ... | 02/11/2003 |
| 6506656 | Stepped collector implant and method for fabrication The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance with a ste... | 01/14/2003 |
| 6504232 | Integrated circuit components thereof and manufacturing method The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or... | 01/07/2003 |
| 6501155 | Semiconductor apparatus and process for manufacturing the same To provide a semiconductor apparatus that secures high ESD protection capability and yet reduces leak current. Cut sections 64-1 and 64-2 are provided in end sections of a second edge 62 of a drain region 22. When a distance between a first edge 60 of a source... | 12/31/2002 |
| 6486532 | Structure for reduction of base and emitter resistance and related method According to one embodiment, a semiconductor device including a base, an emitter, and an emitter contact on top of the emitter is disclosed. For example, the semiconductor device can be a silicon-germanium heterojunction bipolar transistor, in which the b... | 11/26/2002 |
| 6472713 | Semiconductor device having vertical bipolar transistor A semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. The first semiconductor region is a collector region of a first conductivity type. The second sem... | 10/29/2002 |
| 6469366 | Bipolar transistor with collector diffusion layer formed deep in the substrate A semiconductor device allowing reduction in area occupied by a bipolar transistor as well as a method of manufacturing the same are obtained. The semiconductor device includes a substrate, first conductivity type regions, a collector region, base regions... | 10/22/2002 |
| 6440812 | Angled implant to improve high current operation of bipolar transistors Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is a... | 08/27/2002 |
| 6441462 | Self-aligned SiGe NPN with improved ESD robustness using wide emitter polysilicon extension A semiconductor bipolar transistor structure having improved electrostatic discharge (ESD) robustness is provided as well as a method of fabricating the same. Specifically, the inventive semiconductor structure a semiconductor structure comprises a bipola... | 08/27/2002 |
| 6423590 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 07/23/2002 |
| 6414372 | Bipolar transistor having lightly doped epitaxial collector region constant in dopant impurity and process of fabrication thereof A bipolar transistor has a lightly doped n-type single crystal silicon layer epitaxially grown in a recess formed in a heavily doped n-type impurity region after a selective growth of a thick field oxide layer, a base region, an emitter region and a colle... | 07/02/2002 |
| 6406972 | Integrated circuit, components thereof and manufacturing method The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or... | 06/18/2002 |
| 6396126 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 05/28/2002 |
| 6376867 | Heterojunction bipolar transistor with reduced thermal resistance The performance of a heterojunction bipolar transistor (HBT) operating at high power is limited by the power that can be dissipated by the device. This, in turn, is limited by the thermal resistance of the device to heat dissipation. In a typical HBT, and... | 04/23/2002 |
| 6369646 | Leakage current compensation circuit A compensation circuit provides a compensation current to a node of an integrated circuit that experiences increased reverse-bias leakage current between a n-type leaking epitaxial region and a p-type substrate with increased temperature. The compensation... | 04/09/2002 |
| 6365451 | Transistor and method A method of fabricating a semiconductor device and the device. The device is fabricated by providing a substrate having a region thereover of electrically conductive material, and a dielectric first sidewall spacer on the region of electrically conductive... | 04/02/2002 |
| 6352901 | Method of fabricating a bipolar junction transistor using multiple selectively implanted collector regions A process for fabricating a bipolar junction transistor, featuring the use of multiple self-aligned collector regions, used to limit the width of the base region of the transistor, has been developed. The self-aligned collector regions are formed via mult... | 03/05/2002 |
| 6326292 | Semiconductor component and manufacturing method for semiconductor component A semiconductor includes a buried conducting layer, such as a buried collector, comprises a trench, the walls of which are covered with a layer of a material in which dopant ions diffuse faster than in monocrystalline silicon. A contact area is doped in c... | 12/04/2001 |
| 6316817 | MeV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a verticall... | 11/13/2001 |
| 6291304 | Method of fabricating a high voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device)d a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 09/18/2001 |
