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| Number | Title | Issue Date |
| 7385254 | Structure for protection against radio disturbances A structure of protection of a first area of a semiconductor wafer including a substrate of a first conductivity type against high-frequency noise likely to be injected from components formed in the upper portion of a second area of the wafer, includes a very heavil... | 06/10/2008 |
| 7163847 | Method of making circuitized substrate A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric laye... | 01/16/2007 |
| 7091066 | Method of making circuitized substrate A method of making a circuitized substrate in which a commoning bar, used during the plating of the circuitry on the substrate and coupled to a second set of conductors which in turn are coupled to a first set of conductors, is terminated from the second set of cond... | 08/15/2006 |
| 7087943 | Direct alignment scheme between multiple lithography layers A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor. ... | 08/08/2006 |
| 7084014 | Method of making circuitized substrate A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric laye... | 08/01/2006 |
| 6693340 | Lateral semiconductor device A lateral semiconductor device has a semiconductor layer on an insulating layer on a semiconductor substrate. The semiconductor layer has a region of a first conduction type and a region of a second conduction type with a drift region therebetween. The dr... | 02/17/2004 |
| 6693308 | Power SiC devices having raised guard rings Silicon carbide semiconductor power devices having epitaxially grown guard rings edge termination structure are provided. Forming the claimed guard rings from an epitaxially grown SiC layer avoids the traditional problems associated with implantation of g... | 02/17/2004 |
| 6677210 | High voltage transistors with graded extension High voltage transistors with high breakdown voltages are provided. These high voltage transistors are formed with graded drain extension regions. The concentration of charge carriers increases farther away from the gate across each drain extension region... | 01/13/2004 |
| 6677625 | Bipolar transistor The invention provides a bipolar transistor attaining large MSG and a method of fabricating the same. The bipolar transistor of this invention includes a collector layer; abase layer deposited on the collector layer; and a semiconductor layer deposited on... | 01/13/2004 |
| 6674147 | Semiconductor device having a bipolar transistor structure Formed on the surface of an n-type semiconductor layer (21) taken as a collector region is a base region (22) consisting of a p-type region, and formed in the p-type region is an emitter region (23) consisting of an n+ -type region. Further, pr... | 01/06/2004 |
| 6670229 | Bipolar transistor produced using processes compatible with those employed in the manufacture of MOS device A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS trans... | 12/30/2003 |
| 6664610 | Bipolar transistor and the method of manufacturing the same This invention provides a new configuration and manufacturing method of the hetero-junction bipolar transistor. According to the invention, the HBT comprises a semi-insulating InP substrate, a buffer layer on the substrate, a sub-collector layer, a collec... | 12/16/2003 |
| 6664609 | High frequency differential amplification circuit with reduced parasitic capacitance Disclosed is a circuit layout of a differential amplification circuit that constitutes a Gilbert cell, in which two multiple finger bipolar transistors forming a differential amplifier are positioned substantially axially symmetrical to each other. The lo... | 12/16/2003 |
| 6650151 | Process insensitive electronic driver circuitry for integrated RF switching diodes An electronic driver circuitry for an RF switch diode used in Acoustic Ink Jet Printing (AIP) systems is disclosed The electronic driver circuitry consists of a PMOS transistor and a poly resistor used to control the on/off states of the RF switch diode w... | 11/18/2003 |
| 6649985 | Insulated-gate semiconductor device for a rectifier An insulated-gate semiconductor device comprises a source region (S) formed on a predetermined semiconductor substrate such as a ball semiconductor, a drain region (D) formed on the semiconductor substrate at a distance from the source region; and a gate ... | 11/18/2003 |
| 6639277 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 10/28/2003 |
| 6639425 | Process and temperature compensation circuit for integrated RF switching An electronic driver circuitry for an RF switch diode D1 used in Acoustic Ink Jet Printing (AIP) systems that compensates and cancels out undesired variations and non-idealities is disclosed. The electronic driver circuitry consists of a second RF switch ... | 10/28/2003 |
| 6633065 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 10/14/2003 |
| 6630715 | Asymmetrical MOSFET layout for high currents and high speed operation A structure and method for a field effect transistor capable of handling high currents, comprises interleaved source and drain diffusion regions with drain diffusion contacts to a first metal level over the drain diffusions only; while a second metal leve... | 10/07/2003 |
| 6627925 | Transistor having a novel layout and an emitter having more than one feed point A transistor with a novel compact layout is provided. The transistor has an emitter layout having a track with a first feed point and a second feed point whereby current flows through both the first feed point and the second feed point. A base terminal, a... | 09/30/2003 |
| 6617218 | Manufacturing method for semiconductor device A region around the gate of a PMOSFET that does not, at a minimum, affect the transistor characteristics is covered with a resist and a diagonal ion implantation for drain engineering is carried out in a P well region beneath gate electrode. Ions of a fir... | 09/09/2003 |
| 6603176 | Power semiconductor device for power integrated circuit device Provided is a DAD that improves resistance to latch-up and stabilizes breakdown voltage characteristic. Specifically, a first gate electrode (10) and a second drain electrode (13) are linear electrodes having a length not exceeding the length of a source ... | 08/05/2003 |
| 6600206 | High voltage semiconductor device having high breakdown voltage isolation region A high voltage semiconductor device is provided. The high voltage semiconductor device includes a tow voltage region, a high voltage region, and a high breakdown voltage isolation region. The high voltage region is surrounded by the low voltage region and... | 07/29/2003 |
| 6597044 | Semiconductor device having a charge removal facility for minority carriers The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for example the... | 07/22/2003 |
| 6586782 | Transistor layout having a heat dissipative emitter Various embodiments of a novel transistor layout having improved electrical and heat dissipation characteristics are disclosed. Several embodiments include various intrinsic components contoured to the shape of the emitter. The various intrinsic component... | 07/01/2003 |
| 6555894 | Device with patterned wells and method for forming same In a semiconductor substrate having a top surface and a PN junction between a first region of one conductivity type formed by masked diffusion into a semiconductor from the surface and a second region of opposite conductivity type formed into a first port... | 04/29/2003 |
| 6534827 | MOS transistor Ion implantation is conducted using contact holes of a MOS transistor as.a mask to form high concentration diffusion regions, whereby a MOS transistor having a medium withstand voltage structure is provided, in which a high drain withstand voltage, a smal... | 03/18/2003 |
| 6534823 | Semiconductor device A semiconductor body has source and drain regions (4 and 5; 4' and 5') spaced apart by a body region (6; 6') and a drain drift region (50; 50') and both meeting the same surface (3a) of the semiconductor body. An insulated gate structure (7; 70'; 700) is ... | 03/18/2003 |
| 6525383 | Power MOSFET A power MOSFET includes a drain zone which is disposed centrally in a substrate and is annularly surrounded by a lightly doped region of the same conductivity type as the drain zone. The lightly doped region is in turn annularly surrounded by a source zon... | 02/25/2003 |
| 6522203 | Power amplifying transistors In an output stage of an electronic signal processing circuit such as that used for transmission from a mobile telephone set the amplifier circuit comprises two power transistors (A, B) or type FET. The power transistors are used for amplifying different ... | 02/18/2003 |
| 6509585 | Electrostatic discharge protective device incorporating silicon controlled rectifier devices An SCR cell structure provides a plurality of divided p+ and n+ blocks, and varies the spacing, sizes and locations of these divided p+ and n+ blocks to minimize latchup caused by non-ESD events. To further minimize latchup caused by non-ESD events, the S... | 01/21/2003 |
| 6507047 | Power transistors for radio frequencies A field effect transistor is made on a chip comprising a SiC-substrate. The transistor includes a plurality of densely stacked parallel transistor cells occupying totally a rectangular area. Each transistor cell has parallel strip-shaped regions forming t... | 01/14/2003 |
| 6492691 | High integration density MOS technology power device structure High density MOS technology power device structure, including body regions of a first conductivity type formed in a semiconductor layer of a second conductivity type, wherein the body regions include at least one plurality of substantially rectilinear and... | 12/10/2002 |
| 6486512 | Power semiconductor device having high breakdown voltage and method for fabricating the same A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a source structure having a projected portion with a tip-shaped end portion on its center and formed so as to surround a predetermined... | 11/26/2002 |
| 6433370 | Method and apparatus for cylindrical semiconductor diodes Semiconductor diodes are diode connected cylindrical junction field effect devices having one diode terminal as the common connection between a top gate, a back gate and a first channel terminal of the cylindrical junction field effect devices. The second... | 08/13/2002 |
| 6423603 | Method of forming a microwave array transistor for low-noise and high-power applications A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the... | 07/23/2002 |
| 6420225 | Method of fabricating power rectifier device A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type for... | 07/16/2002 |
| 6414370 | Semiconductor circuit preventing electromagnetic noise A semiconductor circuit or a semiconductor device has the current-voltage characteristic that, in a blocking-state of the semiconductor circuit or the semiconductor device, a current gently flows for values of a voltage equal to or greater than a first vo... | 07/02/2002 |
| 6410965 | Annular SCR device A SCR device having at least one annular unit provided on a first type semiconductor substrate. The annular unit comprises a second type well, a first type doping region, a second type contact ring, and a second type doping ring. The second type well is f... | 06/25/2002 |
| 6376898 | Bipolar transistor layout with minimized area and improved heat dissipation An inventive semiconductor integrated circuit device includes multiple transistor banks over a substrate. The banks are arranged to be substantially parallel to each other in a planar layout of the device. Each said bank includes a plurality of unit trans... | 04/23/2002 |
