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| Number | Title | Issue Date |
| 7411251 | Self protecting NLDMOS, DMOS and extended voltage NMOS devices In an NLDMOS, DMOS or NMOS active device the ability to withstand snapback under stress conditions is provided by moving the hot spot away from the drain contact region. This is achieved by moving the drain contact region further away from the gate and including an ... | 08/12/2008 |
| 7400031 | Asymmetrically stressed CMOS FinFET A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ ... | 07/15/2008 |
| 7262447 | Metal oxide silicon transistor and semiconductor apparatus having high λ and β performances A semiconductor apparatus includes a MOS transistor having a semiconductor substrate providing as a channel region between a source and a drain. A gate electrode is formed on the semiconductor substrate via a gate oxide film. A threshold voltage of the source side r... | 08/28/2007 |
| 7262471 | Drain extended PMOS transistor with increased breakdown voltage A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region... | 08/28/2007 |
| 6700175 | Vertical semiconductor device having alternating conductivity semiconductor regions There is provided a method of manufacturing a vertical semiconductor device including a structural section in which an n- -type semiconductor region and a p- -type semiconductor region are arranged alternately without filling trenche... | 03/02/2004 |
| 6696741 | High breakdown voltage PN junction structure, and related manufacturing process PN junction structure including a first junction region of a first conductivity type, and a second junction region of a second conductivity type, wherein between said first and second junction regions a grid of buried insulating material regions is provid... | 02/24/2004 |
| 6693024 | Semiconductor component with a semiconductor body having a multiplicity of pores and method for fabricating The semiconductor component is fabricated on the basis of a semiconductor body with a first and a second surface. A multiplicity of pores are formed in the semiconductor body. The pores extend into the semiconductor body proceeding from the first surface ... | 02/17/2004 |
| 6693338 | Power semiconductor device having RESURF layer A semiconductor device includes a drain layer, first and second drift layers, a RESURF layer, a drain electrode, a base layer, a source layer, a source electrode, and a gate electrode. The first drift layer is formed on the drain layer. The second drift l... | 02/17/2004 |
| 6683356 | Semiconductor device with oxygen doped regions A semiconductor device includes sidewall insulating films formed on sides of the gate electrode layer respectively facing source and drain regions, and silicide layers formed on the source and drain regions. Oxygen-introduced portions are respectively for... | 01/27/2004 |
| 6680243 | Shallow junction formation A method for forming shallow junctions in a substrate. The substrate is masked with a first mask to selectively cover first portions of the substrate and selectively expose second portions of the substrate. A first dopant is implanted substantially within... | 01/20/2004 |
| 6673681 | Process for forming MOS-gated power device having segmented trench and extended doping zone A process for constructing a trench MOS-gated device includes: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the t... | 01/06/2004 |
| 6670658 | Power semiconductor element capable of improving short circuit withstand capability while maintaining low on-voltage and method of fabricating the same In a p-type base layer of a trench IGBT comprising a p-type collector layer, an n-type base layer formed on the p-type collector layer, the p-type base layer formed on the n-type base layer, and an n-type emitter layer formed on the surface of the p-type ... | 12/30/2003 |
| 6670253 | Fabrication method for punch-through defect resistant semiconductor memory device A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting ... | 12/30/2003 |
| 6667516 | RF LDMOS on partial SOI substrate In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, ... | 12/23/2003 |
| 6667213 | Method of fabricating a high-voltage transistor with a multi-layered extended drain structure A method for fabricating a high-voltage transistor with an extended drain region includes forming parallel arranged drift regions, each of which is interleaved with an insulating layer and a conducting layer that functions as a field plate. Source and bod... | 12/23/2003 |
| 6660603 | Higher voltage drain extended MOS transistors with self-aligned channel and drain extensions An integrated circuit drain extension transistor. A transistor gate (72) is formed over a CMOS n-well region (10). A transistor source extension region (50), and drain extension region (52) are formed in the CMOS well region (10). A transistor region (90)... | 12/09/2003 |
| 6649460 | Fabricating a substantially self-aligned MOSFET The present invention includes methods and structures for forming at least a substantially self-aligned MOSFET. According to the present invention, a method of fabricating a semiconductor device includes providing a substrate; providing first materials (s... | 11/18/2003 |
| 6642575 | MOS transistor with vertical columnar structure A field-effect transistor has a vertical columnar structure to restrain a short channel effect without impairing the operating speed of an element. In a semiconductor device having a field-effect transistor with a vertical columnar structure, an n-type di... | 11/04/2003 |
| 6642557 | Isolated junction structure for a MOSFET A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the... | 11/04/2003 |
| 6635544 | Method of fabricating a high-voltage transistor with a multi-layered extended drain structure A method for fabricating a high-voltage transistor with an extended drain region includes forming an epitaxial layer on a substrate, the epitaxial layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair ... | 10/21/2003 |
| 6630699 | Transistor device having an isolation structure located under a source region, drain region and channel region and a method of manufacture thereof The present invention provides a transistor device that does not experience the problems associated with the prior art transistor devices. The transistor device includes a dielectric region located in a trench in a semiconductor substrate and a source reg... | 10/07/2003 |
| 6627515 | Method of fabricating a non-floating body device with enhanced performance A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semicondu... | 09/30/2003 |
| 6605829 | Semiconductor device A DMOS transistor in which a main current flows between first and second main surfaces of a silicon substrate is formed. DMOS transistor has a p-type diffusion region formed in the first main surface, an n+ diffusion region formed in the first ... | 08/12/2003 |
| 6593174 | Field effect transistor having dielectrically isolated sources and drains and method for making same A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semicond... | 07/15/2003 |
| 6580126 | Solid-state relay A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surfac... | 06/17/2003 |
| 6559503 | Transistor with ESD protection The transistor has source and drain diffusion regions between which a gate electrode is disposed. In order to increase the sheet resistance of the source and/or drain diffusion regions, a plurality of strip-shaped insulating zones are provided, which pene... | 05/06/2003 |
| 6548863 | Lateral DMOS transistor integratable in semiconductor power devices The lateral DMOS transistor is integratable in a semiconductor power device comprising a P-type substrate and an N-type epitaxial layer. The lateral DMOS transistor comprises a source region and a drain region formed in the epitaxial layer and a body regi... | 04/15/2003 |
| 6545327 | Semiconductor device having different gate insulating films with different amount of carbon A manufacturing method produces a semiconductor IC device which can maintain a low power consumption for electronic circuits and form gate-isolation layers of different thicknesses without increasing the manufacturing cost. The semiconductor IC device has... | 04/08/2003 |
| 6541343 | Methods of making field effect transistor structure with partially isolated source/drain junctions A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for form... | 04/01/2003 |
| 6528853 | Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors A method and semiconductor structure are provided for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors. A bulk silicon substrate is provided. A deep ion implant layer is implanted to reside below an oxide insulator. An oxyg... | 03/04/2003 |
| 6521946 | Electrostatic discharge resistant extended drain metal oxide semiconductor transistor A semiconductor device comprising a first transistor (40) and a second transistor (100), both formed in a semiconductor substrate (50). The first transistor comprises a gate conductor (56) and a gate insulator (54) separating the gate conductor from a sem... | 02/18/2003 |
| 6518144 | Semiconductor device having trenches and process for same The elements and the trenches are arranged alternately, in repetition, on the main surface of a semiconductor substrate, each of the plurality of elements arranged alternately, in repetition, with the trenches has a configuration (for example, STM) which ... | 02/11/2003 |
| 6518629 | Semiconductor device and process for producing the device In a semiconductor device having high voltage resistance and low ON voltage characteristics, charge-storage regions (insulation layer) are formed in a drift region. Formed above the drift region are a channel region, an emitter region, trench-type gate el... | 02/11/2003 |
| 6518109 | Technique to produce isolated junctions by forming an insulation layer A method for isolating a source and a drain in an MOS transistor by forming an insulation layer adjacent to the source and an insulation layer adjacent to the drain, and an apparatus produced from such a method.... | 02/11/2003 |
| 6498382 | Semiconductor configuration The invention relates to a semiconductor configuration in which electrodes are insulated by a gas-filled or evacuated cavity. The semiconductor configuration includes at least two rigid electrodes; body regions; an active zone; a drift path; and an insula... | 12/24/2002 |
| 6489651 | MOS transistor that inhibits punchthrough A MOS transistor that includes: a semiconductor substrate; a well region formed in the semiconductor substrate, where a trench region is defined in the well region; an isolator formed on a corner of the trench region, where the trench region is filled wit... | 12/03/2002 |
| 6483158 | Semiconductor memory device and fabrication method therefor A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting ... | 11/19/2002 |
| 6476429 | Semiconductor device with breakdown voltage improved by hetero region A power MOSFET includes an n- -drain layer, a drain contact layer disposed on a first side of the drain layer, a p-type base layer disposed on a second side of the drain layer, and an n-source layer disposed on the base layer. A gate electrode ... | 11/05/2002 |
| 6465311 | Method of making a MOSFET structure having improved source/drain junction performance A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in ... | 10/15/2002 |
| 6465852 | Silicon wafer including both bulk and SOI regions and method for forming same on a bulk silicon wafer A silicon substrate comprises a silicon-on-insulator (SOI) portion which includes an insulating silicon dioxide layer beneath a device layer. SOI circuit structures, including SOI field effect transistors, are formed in the device layer. The substrate als... | 10/15/2002 |
