Class 257/E29.02 - Isolation by dielectric regions (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E29.018. This
No. of patents: 180
Last issue date: 10/14/2008

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Number	Title	Issue Date
7436030	Strained MOSFETs on separated silicon layers A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench in...	10/14/2008
7436023	High blocking semiconductor component comprising a drift section A semiconductor component having a drift path (2) which is formed in a semiconductor body (1), is composed of a semiconductor material of first conductance type. The drift path (2) is arranged between at least one first and one second electrode ...	10/14/2008
7423330	Semiconductor device with strain A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed ab...	09/09/2008
7420258	Semiconductor device having trench structures and method In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts. ...	09/02/2008
7417296	Dielectric isolation type semiconductor device A dielectric isolation type semiconductor device can achieve high dielectric resistance while preventing the dielectric strength thereof from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A drift N	08/26/2008
7391095	Semiconductor device In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in co...	06/24/2008
7391077	Vertical type semiconductor device Provided is a semiconductor device including a semiconductor substrate which includes a first semiconductor layer of a first conductivity and a pair of second semiconductor layers disposed on the first semiconductor layer and spaced apart from each other to form a t...	06/24/2008
7378310	Method for manufacturing a memory device having a nanocrystal charge storage region A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. A layer of metal oxide having a first heat of formation is formed on the first...	05/27/2008
7339186	IC chip with nanowires Arrangement of nanowires with PN junctions between bit lines and word lines are arranged as a ROM memory cell array. A number of the nanowires have dielectric regions and are present only as a dummy. The connections between word and bit lines may also exist as trans...	03/04/2008
7323754	Semiconductor device and its manufacture method Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the firs...	01/29/2008
7307320	Differential mechanical stress-producing regions for integrated circuit field effect transistors Integrated circuit field effect transistors include a substrate, an isolation region in the substrate that defines an active region in the substrate, spaced apart source/drain regions in the active region, a channel region in the active region between the spaced apa...	12/11/2007
7301207	Semiconductor device capable of threshold voltage adjustment by applying an external voltage A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surfa...	11/27/2007
7294902	Trench isolation having a self-adjusting surface seal and method for producing one such trench isolation The invention relates to a trench isolation with a self-aligning surface sealing and a fabrication method for said surface sealing. In this case, the surface sealing may have an overlap region of the substrate surface or a receded region into which extends an electr...	11/13/2007
7271068	Method of manufacture of semiconductor device A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film by...	09/18/2007
7268399	Enhanced PMOS via transverse stress In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regio...	09/11/2007
7268402	Memory cell with trench-isolated transistor including first and second isolation trenches An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isola...	09/11/2007
7262486	SOI substrate and method for manufacturing the same The SOI substrate 1 has a supporting substrate 10, an insulating layer 20 formed on the supporting substrate 10 and a silicon layer 30 formed on the insulating layer 20. A through electrode 40 is provided in a device ...	08/28/2007
7235460	Method of forming active and isolation areas with split active patterning A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on t...	06/26/2007
7176101	Method of forming isolation oxide layer in semiconductor integrated circuit device A method is provided in which a first oxide layer is deposited on a silicon substrate and etched to form openings. A first silicon epitaxial layer is grown on the substrate in the openings, forming first active regions, a second oxide layer is deposited thereon, and...	02/13/2007
7129559	High voltage semiconductor device utilizing a deep trench structure A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first po...	10/31/2006
7067923	Semiconductor device having hall-effect and manufacturing method thereof A first insulation film is made of a silicon material and is provided on a semiconductor base. A second insulation film is made of an organic material and is provided on the first insulation film. The second insulation film is thicker than the first insulation film....	06/27/2006
6703671	Insulated gate semiconductor device and method of manufacturing the same Impurity regions 110 that can form an energy barrier are artificially and locally disposed in a channel formation region 111. The impurity regions 110 restrain a depletion layer that extends from a drift region 102 toward a channel formation region 111, a...	03/09/2004
6693024	Semiconductor component with a semiconductor body having a multiplicity of pores and method for fabricating The semiconductor component is fabricated on the basis of a semiconductor body with a first and a second surface. A multiplicity of pores are formed in the semiconductor body. The pores extend into the semiconductor body proceeding from the first surface ...	02/17/2004
6674090	Structure and method for planar lateral oxidation in active An active semiconductor device is made using planar lateral oxidation to define a core region that is surrounded by regions of buried oxidized semiconductor material in. The buried oxidized semiconductor material provides optical waveguiding, and or a def...	01/06/2004
6670260	Transistor with local insulator structure A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The...	12/30/2003
6660571	High voltage power MOSFET having low on-resistance A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift re...	12/09/2003
6661044	Method of manufacturing MOSEFT and structure thereof A method of manufacturing an MOSFET. A substrate is provided. A trench is formed in the substrate. A sacrificial layer is formed to fill the trench. A doped semiconductive layer is formed over the substrate. The doped semiconductive layer is patterned to ...	12/09/2003
6661068	Semiconductor device and method of providing regions of low substrate capacitance A semiconductor structure (1), comprising a isolation region (5) formed on a semiconductor material (10). A pillar (15) is formed in the semiconductor material under the isolation region, where the pillar is capped with a first dielectric material (20) to...	12/09/2003
6642575	MOS transistor with vertical columnar structure A field-effect transistor has a vertical columnar structure to restrain a short channel effect without impairing the operating speed of an element. In a semiconductor device having a field-effect transistor with a vertical columnar structure, an n-type di...	11/04/2003
6635946	Semiconductor device with trench isolation structure A semiconductor device with trench isolation structure is disclosed. The invention uses a trench isolation structure that can be formed by using conventional methods to prevent problems such as drain induced barrier lowering (DIBL), punch-through leakage ...	10/21/2003
6627499	Semiconductor device and method of manufacturing the same Formed in a part of the base region is an impurity diffusion region extending in a vertical direction and having an impurity concentration lower than that in the other portion of the base region. By the formation of the impurity diffusion region, the depl...	09/30/2003
6627949	High voltage power MOSFET having low on-resistance A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift re...	09/30/2003
6624486	Method for low topography semiconductor device formation A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a p...	09/23/2003
6611006	Vertical component peripheral structure A power component formed in an N-type silicon substrate, the lower and upper surfaces of which respectively include a first and a second P-type region that do not extend to the component periphery, a high voltage being capable of existing between the firs...	08/26/2003
6580126	Solid-state relay A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surfac...	06/17/2003
6518134	Method for fabricating a semiconductor device with an air tunnel formed in the lower part of a transistor channel A method for fabricating a semiconductor device, which improves the threshold voltage by forming an air tunnel in the lower part of the transistor channel of a semiconductor device, and also improves the short channel effect by making better the sub-thres...	02/11/2003
6518629	Semiconductor device and process for producing the device In a semiconductor device having high voltage resistance and low ON voltage characteristics, charge-storage regions (insulation layer) are formed in a drift region. Formed above the drift region are a channel region, an emitter region, trench-type gate el...	02/11/2003
6498382	Semiconductor configuration The invention relates to a semiconductor configuration in which electrodes are insulated by a gas-filled or evacuated cavity. The semiconductor configuration includes at least two rigid electrodes; body regions; an active zone; a drift path; and an insula...	12/24/2002
6489211	Method of manufacturing a semiconductor component A method of manufacturing a semiconductor component includes providing a composite substrate (300) with a dielectric portion and a semiconductor portion and growing an epitaxial layer (400) over the composite substrate. The epitaxial layer has a polycryst...	12/03/2002
6489651	MOS transistor that inhibits punchthrough A MOS transistor that includes: a semiconductor substrate; a well region formed in the semiconductor substrate, where a trench region is defined in the well region; an isolator formed on a corner of the trench region, where the trench region is filled wit...	12/03/2002

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Class 257/E29.02 - Isolation by dielectric regions (EPO)