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| Number | Title | Issue Date |
| 7425752 | Semiconductor device channel termination A semiconductor device has a channel termination region for using a trench (30) filled with field oxide (32) and a channel stopper ring (18) which extends from the first major surface (8) through p-well (6) along the outer edge ( | 09/16/2008 |
| 7307330 | Reverse blocking semiconductor device and a method for manufacturing the same A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, w... | 12/11/2007 |
| 6686641 | Semiconductor device and method for driving the same A field oxide surrounding an active region, an N-type doped layer formed in the active region, and an electrode formed on the field oxide in the vicinity of the active region are provided on a P-type semiconductor substrate. During the operation as a cons... | 02/03/2004 |
| 6596615 | Semiconductor device and method of manufacturing the same A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel sto... | 07/22/2003 |
| 6583487 | Power component bearing interconnections A power component formed in an N-type silicon substrate delimited by a P-type wall, having a lower surface including a first P-type region connected to the wall, and an upper surface including a second P-type region, a conductive track extending above the... | 06/24/2003 |
| 6388308 | Semiconductor device and method for driving the same A field oxide surrounding an active region, an N-type doped layer formed in the active region, and an electrode formed on the field oxide in the vicinity of the active region are provided on a P-type semiconductor substrate. During the operation as a cons... | 05/14/2002 |
| 6221724 | Method of fabricating an integrated circuit having punch-through suppression An integrated circuit and method of fabrication is provided for an integrated circuit having punch-through suppression. Unlike conventional methods of punch-through suppression wherein a dopant implant is fabricated in the device, the present invention ut... | 04/24/2001 |
| 6191015 | Method for producing a Schottky diode assembly formed on a semiconductor substrate A Schottky diode assembly includes a Schottky contact formed on a semiconductor substrate and having a semiconductor region of a first conduction type, a metal layer disposed adjacently on the semiconductor region, a protective structure constructed on a ... | 02/20/2001 |
| 6054752 | Semiconductor device A semiconductor device comprises a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer formed on the first semiconductor layer. A unit cell for controlling current... | 04/25/2000 |
| 6025629 | Element isolation structure of a semiconductor device to suppress reduction in threshold voltage of parasitic MOS transistor A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel sto... | 02/15/2000 |
| 5907179 | Schottky diode assembly and production method A Schottky diode assembly includes a Schottky contact formed on a semiconductor substrate and having a semiconductor region of a first conduction type, a metal layer disposed adjacently on the semiconductor region, a protective structure constructed on a ... | 05/25/1999 |
| 5864167 | Semiconductor device In a MOSFET or other high voltage device, an annular channel stopper (4) extends around the outer periphery (14) of a body portion (11) with which a device region (15) forms a p-n junction (5) operable under high reverse bias in at least one mode of opera... | 01/26/1999 |
| 5798562 | Semiconductor device having an isolation layer and two passivation layers with edges that are not aligned with each other The invention relates to a semiconductor device with a substrate, with at least one isolation layer with at least one window, with a passivation layer scheme lying on the isolation layer and a metallization lying on the passivation layer scheme, the latte... | 08/25/1998 |
| 5789269 | Field implant for semiconductor device The concentration of impurities at the surface of the semiconductor device adjacent and under the bird's beak of a field oxide region is reduced by employing sidewall spacers prior to field implantation. The resulting semiconductor device exhibits reduced... | 08/04/1998 |
| 5747354 | Semiconductor device having an improved anti-radioactivity and method of fabricating the same The invention provides an n-channel MOS field effect transistor with an anti-radioactivity. The transistor includes leak guard boron diffusion layers, each of which has a junction surface to an isolation oxide film. The junction surface exists up to a dee... | 05/05/1998 |
| 5723985 | Clocked high voltage switch The present invention discloses methods and apparatus for implementing a clocked high voltage switch involving MOS devices. The switching is from a high voltage source typically at 21V to ground. An intermediate voltage source typically at 11V is introduc... | 03/03/1998 |
| 5723886 | N channel MOSFET with anti-radioactivity The invention provides an n-channel MOS field effect transistor with an improved anti-radioactivity. Such transistor includes a p-type silicon substrate. An isolation oxide film is selectively formed on a surface of the p-type silicon substrate. Source an... | 03/03/1998 |
| 5691233 | Process of forming channel stopper exactly nested in area assigned to thick field oxide layer An obstacle layer is grown on an inner surface of a mask structure defining a first opening over a first area assigned to a thick field oxide layer during a growth of the thick field oxide layer, and prevents a silicon substrate beneath a peripheral area ... | 11/25/1997 |
| 5623154 | Semiconductor device having triple diffusion An isolating/insulating film is formed on the surface of a p- silicon substrate in an element isolating region. An nMOS transistor having a pair of n-type source/drain regions is formed within an element forming region isolated by the isolating... | 04/22/1997 |
| 5604370 | Field implant for semiconductor device The concentration of impurities at the surface of the semiconductor device adjacent and under the bird's beak of a field oxide region is reduced by employing sidewall spacers prior to field implantation. The resulting semiconductor device exhibits reduced... | 02/18/1997 |
| 5571745 | Fabrication method of semiconductor device containing n- and p-channel MOSFETs A fabrication method of an MOS semiconductor device through a reduced number of necessary resist mask formation steps. A patterned resist film is formed on an active region and an isolation insulator film. The resist film has a window exposing the active ... | 11/05/1996 |
| 5559356 | Semiconductor device with large substrate contact region In a MOS-type semiconductor device having a semiconductor substrate, a drain region, a source region, and a gate electrode between the drain region and the source region, a substrate contact region of a conductivity type the same as that of the semiconduc... | 09/24/1996 |
| 5498553 | Method of making a metal gate high voltage integrated circuit A semiconductor is made on a silicon substrate containing an impurity of a predetermined polarity having formed therein a well containing an impurity of an opposite polarity to a region in the silicon is provided. The method comprises forming a first mask... | 03/12/1996 |
| 5289029 | Semiconductor integrated circuit device having wells biased with different voltage levels A semiconductor integrated circuit device is fabricated on a lightly doped n-type substrate, and p-type wells are formed in the silicon wherein a heavily doped n-type channel stopper is formed in a surface portion between the p-type wells for restricting ... | 02/22/1994 |
| 5192993 | Semiconductor device having improved element isolation area A semiconductor device of the present invention is disclosed which includes a semiconductor device of a predetermined conductivity type having a predetermined impurity concentration, a source/drain area formed on the upper surface portion of the semicondu... | 03/09/1993 |
| 5172198 | MOS type semiconductor device A MOS type semiconductor device includes two adjacent MOSFETs. The FETs are respectively formed on element forming areas of a P-type substrate. Each of the transistors has N+ type layers serving as the source and drain thereof and they have a c... | 12/15/1992 |
| 5043778 | Oxide-isolated source/drain transistor A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 formed by using a silicon etch to form a recess, limiting the etched recess with oxide, and backfilling with ... | 08/27/1991 |
| 5043293 | Dual oxide channel stop for semiconductor devices The disclosure relates to oxide-semiconductor interfaces which are grown with varying amounts of fixed positive (or negative) charge. The invention utilizes these different values to form a channel stop for a charge transfer device. For HgCdTe two differe... | 08/27/1991 |
| 5031011 | MOS type semiconductor device A MOS type semiconductor device includes two adjacent MOSFETS. The FETS are respectively formed on element forming areas of a P-type substrate. Each of the transistors has N+ type layers serving as the source and drain thereof they have a commo... | 07/09/1991 |
| 5012312 | Semiconductor integrated circuit and a process for producing the same The impurity concentration in a channel stopper in contact with a second fine active area is selected to be lower than the impurity concentration in a first active area that is wider than the second active area. This prevents the impurity concentration in... | 04/30/1991 |
| 4982247 | Semi-conductor device A semiconductor device, such as a GaAs FET, has low-noise, ultra-high frequency operation. The semiconductor device has at least one bonding pad for applying potential to the gate electrode lying outside of the source region. In practice, one or more bond... | 01/01/1991 |
| 4963502 | Method of making oxide-isolated source/drain transistor A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 are formed by using a silicon etch to form a recess, lining the etched recess with oxide, and backfilling wit... | 10/16/1990 |
| 4960725 | Semiconductor device and manufacturing process for providing device regions on the semiconductor device and isolation regions to isolate the device regions from each other. There is provided a semiconductor device which comprises device regions and isolation regions to isolate the device regions from each other on a semiconductor substrate, wherein field insulators are formed in the isolation regions and conduction layers fo... | 10/02/1990 |
| 4903109 | Semiconductor devices having local oxide isolation A semiconductor monolithic integrated circuit comprising circuit elements built into isolated epitaxial layer islands is described. The isolation is accomplished by part by a p-n junction between the epitaxial layer and its substrate, in part by an insula... | 02/20/1990 |
| 4859616 | Method of making schottky contacts on semiconductor surfaces In a Schottky contact on a semiconductor surface (3) comprising in the semiconductor edge region of the Schottky contact a doped guard ring (7) applied as self-aligning, and in which portions of the semiconductor edge region are shielded by at least one l... | 08/22/1989 |
| 4819045 | MOS transistor for withstanding a high voltage An improved lateral MOS transistor with higher withstand voltage is shown. The transistor is provided with a drift region (19) formed so as to surround a drain region (7) thereof. The curved sections (7b) of the drain region (7) are joined with the drift ... | 04/04/1989 |
| 4754310 | High voltage semiconductor device A field effect transistor, a bipolar transistor, a PIN diode, a Schottky rectifier or other high voltage semiconductor device comprise a semiconductor body having a depletion layer formed throughout a portion in at least a high voltage mode of operation o... | 06/28/1988 |
| 4723155 | Semiconductor device having a programmable fuse element A fuse element is formed on a field insulation film on a semiconductor substrate of n conductivity type in which MOS transistors are formed. A first guard ring region of second conductivity type is provided in the substrate, surrounding the semiconductor ... | 02/02/1988 |
| 4721682 | Isolation and substrate connection for a bipolar integrated circuit A structure for isolating a bipolar transistor (100) from an adjacent transistor includes a first silicon dioxide isolation region (110) laterally surrounding the transistor and a conductive channel stop region (112) laterally surrounding the silicon diox... | 01/26/1988 |
| 4710265 | Method of producing semiconductor integrated circuit having parasitic channel stopper region A complementary MOS type integrated circuit is produced by a method which comprises the steps of: disposing a first mask material layer on the surface of a semiconductor substrate, the first mask material layer having a first impurity introducing region c... | 12/01/1987 |
