Class 257/E27.109 - Using combined field-effect/bipolar structure (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E27.105. This
No. of patents: 35
Last issue date: 07/15/2008

Number	Title	Issue Date
7400024	Formation of deep trench airgaps and related applications A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfille...	07/15/2008
6081004	BiCMOS compacted logic array A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed wit...	06/27/2000
5917342	BiMOS integrated circuit A BiMOS integrated circuit includes a bipolar transistor for output pull-up; a BiMOS hybrid gate buffer section which comprises a MOS transistor for output pull-down which is longitudinally connected to the bipolar transistor, and a MOS transistor for bas...	06/29/1999
5684311	Base cell for BiCMOS and CMOS gate arrays A gate array base cell is disclosed which provides decreased input loading. The preferred base cell comprises two rows of CMOS sites. Each row comprises small CMOS sites CS and large CMOS sites CL. The transistor gates in the small CMOS site CS are narrow...	11/04/1997
5672897	Bimos semiconductor integrated circuit device including high speed vertical bipolar transistors An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface ...	09/30/1997
5629537	Semiconductor device A semiconductor device has a plurality of basic cells fabricated on a single semiconductor substrate. Each of the basic cells comprises a first-conduction-type FETs, a second-conduction-type FETs, and a bipolar transistor. The collector region of the bipo...	05/13/1997
5591995	Base cell for BiCMOS and CMOS gate arrays A gate array base cell is disclosed which provides decreased input loading. The preferred base cell comprises two rows of CMOS sites. Each row comprises small CMOS sites CS and large CMOS sites CL. The transistor gates in the small CMOS site CS are narrow...	01/07/1997
5508549	Semiconductor integrated circuit device and a method for manufacturing the same An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface ...	04/16/1996
5497014	BI-CMOS gate array semiconductor integrated circuits and internal cell structure involved in the same The invention provides a Bi-CMOS gate array semiconductor integrated circuit chip including a peripheral region including an input/output circuit region and a bonding pad region and an internal cell structure provided within an internal cell region involv...	03/05/1996
5444654	ROM with Bi-CMOS gate arrays Disclosed is a semiconductor integrated circuit of a bipolar CMOS gate array type having a plurality of basic cells arranged in a matrix. Each cell comprises MOS transistors as memory cells, a bipolar transistor, a resistance and bit lines, for transferri...	08/22/1995
5398047	Semiconductor integrated circuit device including high-speed operating circuit and low-speed operating circuit, and system using the same The semiconductor integrated circuit device formed on one semiconductor substrate employs a plurality of first and second circuit blocks constituting functions of the same kind. The first and second circuit blocks, however, are implemented with respective...	03/14/1995
5397906	Gate array integrated semiconductor device having stabilized power supply potentials In an unused unit cell of a gate array integrated semiconductor device, a P-type semiconductor region is connected to a ground potential connection and an N-type semiconductor region is connected to a positive power supply connection, thereby reversely-bi...	03/14/1995
5387810	Cell library for semiconductor integrated circuit design A cell library for a semiconductor integrated circuit design, comprises a CMOS cell comprising two power source wires and a CMOS circuit placed between the two power source wires at a predetermined distance, and a BiCMOS cell comprising two power source w...	02/07/1995
5378941	Bipolar transistor MOS transistor hybrid semiconductor integrated circuit device A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input sign...	01/03/1995
5341041	Basic cell for BiCMOS gate array An improved cell for use in a mask programmable gate array is disclosed herein. The preferred cell comprises two compute sections, each comprising two pairs of medium size P and N-channel transistors, two small N-channel transistors, and a single small P-...	08/23/1994
5289021	Basic cell architecture for mask programmable gate array with 3 or more size transistors A highly efficient CMOS cell structure for use in a metal mask programmable gate array, such as a sea-of-gates type gate array, is disclosed herein. In a basic cell, in accordance with one embodiment of the invention, three or more sizes of N-channel tran...	02/22/1994
5281545	Processes for manufacturing a semiconductor device A Bi-CMOS ( Bipolar-Complementary Metal Oxide Silicon ) gate array includes bipolar transistors, and P-channel and N-channel MOS transistors all formed on the same single chip in the form of an array. Such a chip may provide desired bipolar and MOS transi...	01/25/1994
5278436	Semiconductor integrated circuit device for forming logic circuit including resistance element connected to bipolar transistor with smaller occupied area Disclosed is an improved Bi-CMOS gate array for increasing integration density. The gate array includes a predetermined region for forming PMOS transistors, a predetermined region for forming bipolar transistors, a predetermined region for forming resista...	01/11/1994
5272366	Bipolar transistor/insulated gate transistor hybrid semiconductor device A bipolar transistor/insulated gate transistor hybrid semiconductor device comprises a well region formed on a semiconductor substrate to serve as a first active region of a bipolar transistor, an insulated gate transistor having source and drain regions ...	12/21/1993
5220187	Semiconductor integrated circuit with bipolar transistors and MOSFETs A logic circuit to be formed in a gate array is selected depending upon the value of the output load capacitance thereof, from among a CMOS circuit, a first Bi-CMOS circuit including an output bipolar transistor whose emitter size is set at a predetermine...	06/15/1993
5187555	Semiconductor integrated circuit of standard cell system Transistor elements which are not initially wired are previously arranged in no-cell regions created in part of cell array regions in a standard cell layout according to the layout design. When the circuit is changed in the standard cell layout, a desired...	02/16/1993
5168342	Semiconductor integrated circuit device and manufacturing method of the same In a semiconductor integrated circuit device adopting a master slice system, a plurality of lattice points of an X-Y lattice-shaped channel region set by an automatic arrangement and routing system correspond to one input/output terminal of a prescribed b...	12/01/1992
5119314	Semiconductor integrated circuit device A semiconductor integrated circuit device which can operate at high speed and involves a low power consumption and a high integration density, wherein a Bi-CMOS basic cell and a Bi-CMOS macro cell are employed to define a critical path and a CMOS basic ce...	06/02/1992
5107147	Base cell for semi-custom circuit with merged technology A BiCMOS gate array base is disclosed which is capable of simultaneously implementing a BiCMOS gate and/or a multitude of CMOS gates. The cell has symmetry about 1 axis, with the bipolar devices in the center and equally accessible for interconnect by two...	04/21/1992
5101258	Semiconductor integrated circuit device of master slice approach In a semiconductor integrated circuit device of master slice approach according to this invention, regions on basic elements which are not used and isolation areas serve as wiring regions. Resistive elements are formed on the regions on the basic elements...	03/31/1992
5072285	Semiconductor integrated circuit having region for forming complementary field effect transistors and region for forming bipolar transistors A Bi-CMOS gate array comprises basic cells combining CMOS transistors and bipolar transistors. The basic cell is formed of a region for forming p-MOS transistors, a region for forming n-MOS transistors and a region for forming bipolar transistors. The reg...	12/10/1991
5066996	Channelless gate array with a shared bipolar transistor A semiconductor device is disclosed having a channelless gate array. A plurality of standard cells are formed on a gate array chip such that one of the standard cells is formed relative to the adjacent standard cell with a bipolar transistor and resistor ...	11/19/1991
5055716	Basic cell for BiCMOS gate array An improved cell for use in a mask programmable gate array is disclosed herein. The preferred cell comprises two compute sections, each comprising two pairs of medium size P and N-channel transistors, two small N-channel transistors, and a single small P-...	10/08/1991
5049967	Semiconductor integrated circuit device and a method for manufacturing the same An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from a surface to...	09/17/1991
5031019	Method for manufacturing a semiconductor device having isolated islands and its resulting structure A method for manufacturing a Bi-CMOS device by preparing both of bipolar and MOS standard cells in a library is provided. A substrate of a first conductivity type is provided and a plurality of buried layers of a second conductivity type are formed on sel...	07/09/1991
5028978	Complementary bipolar complementary CMOS (CBiCMOS) transmission gate A CBiCMOS transmission gate in which the sources of a CMOS transistor pair are connected to an input and the drains are connected to the bases of a complementary bipolar transistor pair. The bipolar transistor pair is serially connected between a plus vol...	07/02/1991
5001487	Semiconductor integrated circuit device A semiconductor integrated circuit device is disclosed. The circuit device uses modified (m+n) input cells, each equipped with high load driving functional elements disposed at the periphery of the cell, and having n signal input terminal(s) in addition t...	03/19/1991
4980744	Semiconductor integrated circuit device and a method for manufacturing the same An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface ...	12/25/1990
4921811	Semiconductor integrated circuit device and a method for manufacturing the same An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface ...	05/01/1990
4682202	Master slice IC device A master slice IC device comprising at least two kind of basic cells; that is, a first kind of basic cells each having one or more n-type MIS transistors and one or more p-type MIS transistors to form a CMIS logic circuit, and a second kind of basic cells...	07/21/1987

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Class 257/E27.109 - Using combined field-effect/bipolar structure (EPO)