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| Number | Title | Issue Date |
| 7439132 | Semiconductor device comprising capacitor and method of fabricating the same A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. ... | 10/21/2008 |
| 7410864 | Trench and a trench capacitor and method for forming the same A method for fabricating a trench includes providing a semiconductor substrate made of a semiconductor material. A trench is etched into a surface of the semiconductor substrate such that a trench wall is produced. At least one layer is provided on the trench wall. ... | 08/12/2008 |
| 7407852 | Trench capacitor of a DRAM and fabricating method thereof A method of fabricating trench capacitors is described. A substrate having at least one isolation structure is provided. A first trench and a second trench are formed in the substrate beside the isolation structure. A first lower electrode and a second lower electro... | 08/05/2008 |
| 7405122 | Methods for fabricating a capacitor A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mas... | 07/29/2008 |
| 7402859 | Field effect semiconductor switch and method for fabricating it A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the surface of the semiconductor layer, an insulating layer between the fir... | 07/22/2008 |
| 7391070 | Semiconductor structures and memory device constructions The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and ... | 06/24/2008 |
| 7387930 | Method of fabricating a bottle trench and a bottle trench capacitor A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substr... | 06/17/2008 |
| 7355234 | Semiconductor device including a stacked capacitor A stacked capacitor formed in a capacitor hole includes a bottom electrode, capacitor insulation film and a top electrode. The bottom electrode includes a plurality of islands formed on an underlying insulating film, and a metallic film covering the islands on the u... | 04/08/2008 |
| 7351634 | Trench-capacitor DRAM device and manufacture method thereof A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adja... | 04/01/2008 |
| 7348235 | Semiconductor device and method of manufacturing the same An isolation insulation film is formed in an isolation trench in an upper portion of a silicon substrate. The isolation insulation film has an opening by which inner walls and bottom of the isolation trench are exposed. A lower diffusion layer serving as a lower ele... | 03/25/2008 |
| 7348596 | Devices for detecting current leakage between deep trench capacitors in DRAM devices A test device for detecting current leakage between deep trench capacitors in DRAM devices. The test device is disposed in a scribe line region of a wafer. In the test device, a first trench capacitor pair has a first deep trench capacitor and a second deep trench c... | 03/25/2008 |
| 7344953 | Process for vertically patterning substrates in semiconductor process technology by means of inconformal deposition On a substrate surface, which has been patterned in the form of a relief, of a substrate, typically of a semiconductor wafer, a deposition process is used to provide a covering layer on process surfaces which are vertical or inclined with respect to the substrate su... | 03/18/2008 |
| 7342274 | Memory cells with vertical transistor and capacitor and fabrication methods thereof Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The firs... | 03/11/2008 |
| 7339224 | Trench capacitor and corresponding method of production The invention relates to a trench capacitor, in particular for use in a semiconductor memory cell, comprising a trench (2), embodied in a substrate (1), a first region (1a), provided in the substrate (1), as first capacitor electro... | 03/04/2008 |
| 7326986 | Trench memory A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the tren... | 02/05/2008 |
| 7321149 | Capacitor structures, and DRAM arrays A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking lay... | 01/22/2008 |
| 7321147 | Semiconductor device including a trench capacitor A device including a trench capacitor formed in a semiconductor substrate for configuring a DRAM cell together with a cell transistor is provided. The device also includes a cell transistor including diffused regions formed in a surface of a semiconductor substrate;... | 01/22/2008 |
| 7315054 | Decoupling capacitor density while maintaining control over ACLV regions on a semiconductor integrated circuit In one embodiment, a method of controlling the across-chip line-width variation (ACLV) on a semiconductor integrated circuit includes forming an ACLV controlled region including a plurality of semiconductor devices each having a gate structure and arranging the plur... | 01/01/2008 |
| 7301192 | Dram cell pair and dram memory cell array Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two sele... | 11/27/2007 |
| 7298019 | Capacitor of semiconductor device and method of manufacturing the same A MIM capacitor includes a lower electrode disposed on a semiconductor substrate. A dielectric layer is disposed on the lower electrode to completely cover an exposed surface of the lower electrode. An upper electrode is disposed on the dielectric layer. A method fo... | 11/20/2007 |
| 7265020 | Semiconductor device with DRAM cell and method of manufacturing the same A method of manufacturing a semiconductor device includes forming a trench in a semiconductor substrate, isotropically forming a trench surface insulating film on an inner surface of the trench, the trench surface insulating film including a deep part functioning as... | 09/04/2007 |
| 7262452 | Method of forming DRAM device having capacitor and DRAM device so formed In a method of forming a DRAM device having a capacitor and a DRAM device so formed, an interlayer dielectric having at least one layer is formed on a semiconductor substrate. The interlayer dielectric layer and a predetermined portion of the semiconductor substrate... | 08/28/2007 |
| 7256440 | Semiconductor memory cell having a trench and a planar selection transistor and method for producing the same A trench (12) of a semiconductor memory cell (1) has an insulation collar (44), which is open toward the substrate (42) on just one side (50). On the other side (52), the insulation collar (44, 47, 55) rises all the w... | 08/14/2007 |
| 7250336 | Method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure The present invention provides a method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure, comprising the steps of: providing a trench in the microelectronic or micromechanical structure; providing a partial filling in the t... | 07/31/2007 |
| 7247536 | Vertical DRAM device with self-aligned upper trench shaping A method and structure for a memory storage cell in a semiconductor substrate includes forming a dopant source material over a lower portion of a deep trench formed in the substrate. An upper portion of the trench is shaped to a generally rectangular configuration, ... | 07/24/2007 |
| 7232735 | Semiconductor device having a cylindrical capacitor and method for manufacturing the same using a two-layer structure and etching to prevent blockage A semiconductor device according to the present invention includes a cylindrical capacitor. An amorphous silicon layer serving as a lower electrode of the cylindrical capacitor has a two-layer structure including a lower high-concentration impurity sublayer and an u... | 06/19/2007 |
| 7223653 | Process for forming a buried plate A method is provided for making a buried plate region in a semiconductor substrate. According to such method, a trench is formed in a semiconductor substrate, the trench having a trench sidewall, the sidewall including an upper portion, and a lower portion disposed ... | 05/29/2007 |
| 7214982 | Semiconductor memory device and method of manufacturing the same A semiconductor device including a ferroelectric random access memory, which has a structure suitable for miniaturization and easy to manufacture, and having less restrictions on materials to be used, comprises a field effect transistor formed on a surface area of a... | 05/08/2007 |
| 7208789 | DRAM cell structure with buried surrounding capacitor and process for manufacturing the same A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and... | 04/24/2007 |
| 7205567 | Semiconductor product having a semiconductor substrate and a test structure and method A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an inner capacitor electrode of a trench capacitor by a dopant diffusion region with an interconnect is discl... | 04/17/2007 |
| 7157766 | Variable capactor structure and method of manufacture A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped... | 01/02/2007 |
| 7138677 | Capacitor arrangement with capacitors arranged one in the other Arrangement of capacitors which, without taking up an additional area in the semiconductor substrate, have an increased capacitance compared with conventional capacitors in DRAM memory cells. The arrangement of capacitors according to the invention is based on a com... | 11/21/2006 |
| 7126154 | Test structure for a single-sided buried strap DRAM memory cell array A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory ce... | 10/24/2006 |
| 7122855 | Semiconductor memory device and method of manufacturing the same A semiconductor memory device includes a trench formed in the semiconductor substrate, a diffusion layer for a first electrode formed within the semiconductor substrate so as to be in contact with an inner surface of the trench, a capacitor insulating film formed on... | 10/17/2006 |
| 7115932 | Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same A semiconductor device and its method of fabrication are provided. The semiconductor device includes a substrate, a patterning stop region, an insulating overlayer, a container region within the insulating overlayer, a charge storage lamina or conductive layer over ... | 10/03/2006 |
| 7115935 | Embedded DRAM for metal-insulator-metal (MIM) capacitor structure A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a log... | 10/03/2006 |
| 7091541 | Semiconductor device using a conductive film and method of manufacturing the same A semiconductor device has a capacitive element including a first conductive film formed on the bottom and wall surfaces of an opening formed in an insulating film on a substrate, a dielectric film formed on the first conductive film, and a second conductive film fo... | 08/15/2006 |
| 7078289 | Method for fabricating a deep trench capacitor of DRAM device A method for fabricating a deep trench capacitor of DRAM devices is disclosed. A substrate with a deep trench formed therein is provided. The trench is then doped to form a buried plate electrode serving as a first electrode of the deep trench capacitor at a lower p... | 07/18/2006 |
| 7071054 | Methods of fabricating MIM capacitors in semiconductor devices Methods of fabricating an MIM capacitor and a dual damascene structure of a semiconductor device are disclosed. According to one example, a method includes depositing a first insulating layer on a semiconductor substrate; forming a lower interconnect through the fir... | 07/04/2006 |
| 6696335 | Method for forming a diffusion region For particularly simple and targeted formations of a diffusion region, an interfacial region of a semiconductor substrate is subjected to a thermal transformation process and thereby carry out the thermally activated diffusion of a dopant in a substantial... | 02/24/2004 |
