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| Number | Title | Issue Date |
| 7442979 | Reduced cell-to-cell shorting for memory arrays Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The... | 10/28/2008 |
| 7413951 | Stacked capacitor and method for producing stacked capacitors for dynamic memory cells A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42... | 08/19/2008 |
| 7259414 | Integrated circuit, its fabrication process and memory cell incorporating such a circuit This integrated circuit comprises a capacitor (23) formed above a substrate (1) inside a first cavity in a dielectric and comprising a first electrode, a second electrode, a thin dielectric layer placed between the two electrodes, and a structure (7... | 08/21/2007 |
| 7112840 | Semiconductor memory device and method for fabricating the same The present invention relates to a semiconductor memory device and a method for fabricating the same. Particularly, the semiconductor memory device includes at least more than two capacitors to decrease the thickness of an insulation layer and increase the size of e... | 09/26/2006 |
| 6699745 | Capacitor and memory structure and method A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.... | 03/02/2004 |
| 6696351 | Semiconductor device having a selectively deposited conductive layer A process of production of a semiconductor memory device having a memory array including memory cells and a peripheral circuit on one substrate comprising the process of forming an interlayer insulating layer covering the memory array and peripheral circu... | 02/24/2004 |
| 6673671 | Semiconductor device, and method of manufacturing the same There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the... | 01/06/2004 |
| 6667502 | Structurally-stabilized capacitors and method of making of same Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which... | 12/23/2003 |
| 6649956 | Semiconductor integrated circuit device and manufacturing method thereof An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends ... | 11/18/2003 |
| 6638817 | Method for fabricating dram cell array not requiring a device isolation layer between cells The present invention relates to a DRAM cell array and a fabrication method thereof, and which includes: a semiconductor substrate on which a plurality of active regions and isolation regions in a rectangular strip shape at a predetermined distance from e... | 10/28/2003 |
| 6630380 | Method for making three-dimensional metal-insulator-metal capacitors for dynamic random access memory (DRAM) and ferroelectric random access memory (FERAM) A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant or ferroelectric interelectrode films compatible with the dual-damascene process is achieved. The method of integrating the MIM with a dual-damascen... | 10/07/2003 |
| 6624018 | Method of fabricating a DRAM device featuring alternate fin type capacitor structures A process for fabricating an alternate fin type capacitor structure, used to increase capacitor surface area has been developed. The process features the formation of fin shaped, storage node structures, located in fin type capacitor openings, which are i... | 09/23/2003 |
| 6620674 | Semiconductor device with self-aligned contact and its manufacture A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the sec... | 09/16/2003 |
| 6599840 | Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi... | 07/29/2003 |
| 6596642 | Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi... | 07/22/2003 |
| 6596648 | Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi... | 07/22/2003 |
| 6580114 | Processing methods of forming a capacitor, and capacitor construction Capacitors and methods of forming capacitors are described. According to one implementation, a capacitor opening is formed over a substrate node location. Electrically conductive material is subsequently formed within the capacitor opening and makes an el... | 06/17/2003 |
| 6528369 | Layer structure having contact hole and method of producing same A dynamic random access memory (DRAM) device includes a stacked capacitor including a storage electrode, a dielectric film and a cell plate. In a preferred embodiment, the storage electrode contacts with a diffusion region of a substrate through a contact... | 03/04/2003 |
| 6518611 | Capacitor array structure for semiconductor devices Exemplary embodiments of the present invention teach a structure and process for forming an array of storage capacitors by forming a first set of individual storage node plates, forming alternating storage node pillars, forming a second set of individual ... | 02/11/2003 |
| 6514819 | High capacity stacked DRAM device and process for making a smaller geometry A DRAM having a theoretical cell layout efficiency of 100% and a density of up to four gigabits DRAM is obtained without sacrificing the storage capacitor values. This accomplishment is achieved by introducing landing pads in layout and obtaining narrow w... | 02/04/2003 |
| 6512259 | Capacitor with high-&3xb5; dielectric or ferroelectric material based on the fin stack principle A capacitor in a semiconductor configuration on a substrate includes a noble-metal-containing first capacitor electrode which is formed with a plurality of mutually spaced-apart lamellae. The lamellae are oriented substantially parallel to a surface of th... | 01/28/2003 |
| 6507065 | Doped silicon structure with impression image on opposing roughened surfaces A silicon structure is formed that includes a free-standing wall having opposing roughen ed inner and outer surfaces using ion implantation and an unplanted silicon etching process which is selective to implanted silicon. In general, the method provides a... | 01/14/2003 |
| 6483136 | Semiconductor integrated circuit and method of fabricating the same An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends ... | 11/19/2002 |
| 6472704 | Semiconductor device having contact hole and method of manufacturing the same A semiconductor device is obtained which allows a simpler formation process of a capacitor contact hole and reduction in capacitance between bit interconnections. A first capacitor contact hole is formed in a silicon nitride film and an interlayer insulat... | 10/29/2002 |
| 6461967 | Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi... | 10/08/2002 |
| 6441424 | Integrated circuit configuration having at least one capacitor and method for producing the same An integrated circuit configuration, in particular is a DRAM cell configuration, includes a capacitor disposed on a first substrate and a portion with a contact disposed on a second substrate. The first substrate is connected to the second substrate, with... | 08/27/2002 |
| 6432771 | DRAM and MOS transistor manufacturing A method of manufacturing DRAM cells in a substrate, including the steps of: depositing a first conductor in first openings in a first insulator partially exposing source/drain regions; opening a second insulator to partially expose the first openings con... | 08/13/2002 |
| 6417040 | Method for forming memory array having a digit line buried in an isolation region A memory array includes a semiconductor substrate, an isolation trench disposed in the substrate, and a conductor that is disposed in the trench. The array also includes a memory cell that is coupled to the conductor in the trench. The conductor may be a ... | 07/09/2002 |
| 6413831 | Method of fabrication for a honeycomb capacitor A honeycomb/webbed, high surface area capacitor formed by etching a storage poly using an etch mask having a plurality, of micro vias. The etch mask is preferably formed by applying an HSG polysilicon layer on a surface of the storage poly with a mask lay... | 07/02/2002 |
| 6399433 | Method for fabricating a memory cell A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one... | 06/04/2002 |
| 6399439 | Method for manufacturing semiconductor device Disclosed herein is a method for manufacturing a semiconductor device in which a hemispherical grain size of an inner and an outer wall surfaces of a cylindrical member is uniform to promote the increase of surface areas and to prevent short-circuit betwe... | 06/04/2002 |
| 6385020 | Methods of forming HSG capacitors from nonuniformly doped amorphous silicon layers and HSG capacitors formed thereby A hemispherical grain (HSG) capacitor having HSGs on at least a part of the surface of capacitor lower electrodes, and a method of forming the same. In the capacitor, lower electrodes are formed of at least two amorphous silicon layers including an amorph... | 05/07/2002 |
| 6380574 | Ferroelectric capacitor with a self-aligned diffusion barrier A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layers of a switching transistor is self-aligned. As a result, no side trench is produced ... | 04/30/2002 |
| 6373084 | Shared length cell for improved capacitance A container capacitor having an elongated storage electrode for enhanced capacitance in a dynamic random access memory circuit. The electrode is preferably twice the length of the typical cell and may be coated with hemispherical-grain polysilicon to furt... | 04/16/2002 |
| 6355520 | Method for fabricating 4F2 memory cells with improved gate conductor structure In accordance with the present invention, a method for forming gate conductors in 4F2 area stacked capacitor memory cells includes the steps of forming a buried bit line in a substrate, forming an active area above and in contact with the burie... | 03/12/2002 |
| 6340619 | Capacitor and method of fabricating the same A capacitor includes a substrate, an insulating layer on the substrate, the insulating layer having a contact hole, a first storage node in the contact hole and on the insulating layer, a second storage node on a peripheral portion of the first storage no... | 01/22/2002 |
| 6333226 | Method of manufacturing semiconductor memory device having a capacitor Disclosed herein is a semiconductor memory device. In the semiconductor memory device, a transfer transistor having a drain region and a source region is formed on an Si semiconductor substrate. A lower end of a storage node is electrically connected to t... | 12/25/2001 |
| 6331720 | Electrically conductive structure An electrically conductive structure, such as a capacitor is disclosed. A capacitor can be made by providing a space extending between a pair of gate stacks on a semiconductor substrate, the space exposing a charge conducting region on the semiconductor s... | 12/18/2001 |
| 6323080 | Conductive electrical contacts, capacitors, DRAMs, and integrated circuitry, and methods of forming conductive electrical contacts, capacitors, DRAMs, and integrated circuitry The invention encompasses DRAM constructions, capacitor constructions, conductive contacts, integrated circuitry, methods of forming DRAM constructions, and methods of forming capacitor constructions. The invention includes a method of forming a contact t... | 11/27/2001 |
| 6316312 | Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures Semiconductor capacitor constructions, DRAM cell constructions, methods of forming semiconductor capacitor constructions, methods of forming DRAM cell constructions, and integrated circuits incorporating capacitor structures and DRAM cell structures are e... | 11/13/2001 |
