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| Number | Title | Issue Date |
| 7439134 | Method for process integration of non-volatile memory cell transistors with transistors of another type A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method inc... | 10/21/2008 |
| 7436043 | N-well and Nburied layer isolation by auto doping to reduce chip size A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the com... | 10/14/2008 |
| 7436036 | PMOS transistor of semiconductor device, semiconductor device comprising the same, and method for manufacturing the same A PMOS transistor of a semiconductor device exhibiting improved characteristics, a semiconductor device incorporating the same, and a method for manufacturing the semiconductor device. The PMOS transistor incorporates a first gate insulation film formed in a predete... | 10/14/2008 |
| 7423303 | Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating laye... | 09/09/2008 |
| 7408228 | Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type... | 08/05/2008 |
| 7390709 | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part t... | 06/24/2008 |
| 7381989 | Semiconductor device including upper and lower transistors and interconnection between upper and lower transistors A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film ov... | 06/03/2008 |
| 7378713 | Semiconductor devices with dual-metal gate structures and fabrication methods thereof Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped r... | 05/27/2008 |
| 7378318 | System and method for ensuring migratability of circuits by masking portions of the circuits while improving performance of other portions of the circuits A system and method for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress ... | 05/27/2008 |
| 7375409 | Semiconductor device including transistors having different drain breakdown voltages on a single substrate A semiconductor device is provided comprising a supporting substrate, an insulating layer on the substrate, and a first semiconductor layer on the insulating layer. A first high breakdown-voltage transistor is formed in the first semiconductor layer, a second semico... | 05/20/2008 |
| 7365392 | Semiconductor device with integrated trench lateral power MOSFETs and planar devices Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same... | 04/29/2008 |
| 7361932 | Semiconductor device and method for fabricating the same A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a... | 04/22/2008 |
| 7345346 | Field effect transistor having contact plugs in the source region greater than in the drain region A semiconductor device having a field effect transistor formed on a semiconductor layer on an insulator, comprising: a drain electrode wiring formed over a drain region of the field effect transistor; a source electrode wiring formed over a source region of the fiel... | 03/18/2008 |
| 7342287 | Power gating schemes in SOI circuits in hybrid SOI-epitaxial CMOS structures Disclosed are a multi-threshold CMOS circuit and a method of designing such a circuit. The preferred embodiment combines an MTCMOS scheme and a hybrid SOI-epitaxial CMOS structure. Generally, the logic transistors (both nFET and pFET) are placed in SOI, preferably i... | 03/11/2008 |
| 7335561 | Semiconductor integrated circuit device and manufacturing method thereof After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after tha... | 02/26/2008 |
| 7314797 | Semiconductor device and its manufacturing method A semiconductor device is capable of being applied with both a positive and a negative voltage to its control gate, and writing to its memory requires a low voltage. A control gate is formed on a memory unit region of a field oxide film, and an inter-layer silicon o... | 01/01/2008 |
| 7285798 | CMOS inverter constructions Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active region extending into both a strained crystalline lattice and a relaxed ... | 10/23/2007 |
| 7285838 | Semiconductor device and method of manufacturing the same A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, | 10/23/2007 |
| 7279727 | Semiconductor device A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate... | 10/09/2007 |
| 7273787 | Method for manufacturing gate dielectric layer A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region... | 09/25/2007 |
| 7271414 | Semiconductor device and method for fabricating the same A semiconductor device includes a transistor of a first conductivity type and a transistor of a second conductivity type. The transistor of the first conductivity type includes a first gate portion formed on a first region of a semiconductor substrate, a first sidew... | 09/18/2007 |
| 7253045 | Selective P-channel Vadjustment in SiGe system for leakage optimization A method of manufacturing a semiconductor device includes forming a silicon germanium layer and a N-channel transistor and a P-channel transistor over the silicon germanium layer. A beta ratio of the N-channel transistor to the P-channel transistor is about 1.8 to a... | 08/07/2007 |
| 7224037 | Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions o... | 05/29/2007 |
| 7217607 | Method for manufacturing semiconductor integrated circuit device In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is su... | 05/15/2007 |
| 7217985 | Semiconductor device including a transistor having low threshold voltage and high breakdown voltage A semiconductor device, including a transistor having low threshold voltage and high breakdown voltage, includes a first gate electrode, a second gate electrode, and a third gate electrode arranged on a predetermined first, second, and third region of a semiconducto... | 05/15/2007 |
| 7196393 | Semiconductor device including a high voltage transistor A drain diffusion layer 11b includes a low impurity concentration region 5a and a high impurity concentration region 5b, and the low impurity concentration region 5a is located on the channel region side. An im... | 03/27/2007 |
| 7172935 | Method of forming multiple gate insulators on a strained semiconductor heterostructure A method for forming multiple gate insulators on a strained semiconductor heterostructure, including the steps of oxidation and deposition. ... | 02/06/2007 |
| 7091563 | Method and structure for improved MOSFETs using poly/silicide gate height control A method for manufacturing an integrated circuit that has a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor. This method involves depositing oxide fill on the n-type transistor and the p-type transi... | 08/15/2006 |
| 7087969 | Complementary field effect transistor and its manufacturing method A complementary field effect transistor comprises: a semiconductor substrate; an n-type field effect transistor provided on the semiconductor substrate; and a p-type field effect transistor provided on the semiconductor substrate. The n-type field effect transistor ... | 08/08/2006 |
| 7081656 | CMOS constructions The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 Å (or alternatively comprising a thickness resulting from no more than 70 ALD cycles) is formed between conductively-doped silicon and ... | 07/25/2006 |
| 7071527 | Semiconductor element and manufacturing method thereof A p-channel MOSFET (1) includes a semiconductor substrate (2), an epitaxial region (3), a second diffusion region (6), and a drain region. The epitaxial region (3) is formed on the upper surface of the semiconductor substrate (2... | 07/04/2006 |
| 7045410 | Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI) A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is th... | 05/16/2006 |
| 7005339 | Method of integrating high voltage metal oxide semiconductor devices and submicron metal oxide semiconductor devices The present invention provides a method of integrating at least one high voltage metal oxide semiconductor device and at least one Submicron metal oxide semiconductor device on a substrate. The method comprises: providing the substrate, forming a plurality of shallo... | 02/28/2006 |
| 6703670 | Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention ... | 03/09/2004 |
| 6674114 | Semiconductor device and manufacturing method thereof In a semiconductor device having P type and N type wells formed bordering on a step on a P type semiconductor substrate, a first transistor (precise transistor) having a first linewidth is formed on the P type well in a step lower region while a second tr... | 01/06/2004 |
| 6670694 | Semiconductor device A surface orientation other than a (100) surface orientation is exposed to the surface portion of a silicon substrate having the (100) surface orientation, for example. A silicon epitaxial growth layer is formed only on a region containing a channel formi... | 12/30/2003 |
| 6661061 | Integrated circuit with differing gate oxide thickness A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with res... | 12/09/2003 |
| 6642543 | Thin and thick gate oxide transistors on a functional block of a CMOS circuit residing within the core of an IC chip A functional block for a CMOS circuit within the core of an integrated circuit chip and a method of making the same is disclosed. The functional block uses both thick and thin gate oxide transistors which reduces the leakage current and increases the volt... | 11/04/2003 |
| 6621125 | Buried channel device structure A buried channel device structure for an electrostatic discharge protection circuit capable of minimizing the effect on the electrostatic discharge protection circuit due to current flowing close to gate oxide layer. A p+ ion-doped region is formed above ... | 09/16/2003 |
| 6611027 | Protection transistor with improved edge structure A metal-oxide-semiconductor protection transistor is formed in an active region of a semiconductor layer. The active region includes source and drain diffusion layers, which may be partly silicided, and a body region. A gate electrode extends across the a... | 08/26/2003 |