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Wearable Device For Feeding and Observing Birds and Other Flying Animals
A device for feeding and observing flying animals comprising a hat, a support mounted on the hat and extending outward from the hat, and a feeder mounted on the support.
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| Number | Title | Issue Date |
| 5495122 | Insulated-gate semiconductor field effect transistor which operates with a low gate voltage and high drain and source voltages In a low voltage drive circuit section of a semiconductor integrated circuit, the gate oxide films are approximately 250 Å, and a low voltage N-channel IGFET and a low voltage P-channel IGFET are operable at high speed and driven at a low voltage. In a h... | 02/27/1996 |
| 5488249 | Differential analog transistors constructed from digital transistors The invention concerns approaches to interconnecting individual field-effect transistors (FETs) in integrated circuits (ICs), in order to provide a larger, composite transistor. In one approach, the individual FETs are positioned symmetrically about centr... | 01/30/1996 |
| 5474952 | Process for producing a semiconductor device A process for producing a semiconductor service of the type having a semiconductor substrate; a semiconductor layer disposed on the semiconductor substrate; a first element formed in a region of the semiconductor layer and having a perimeter including a b... | 12/12/1995 |
| 5472887 | Method of fabricating semiconductor device having high-and low-voltage MOS transistors A semiconductor device (76) is provided with a high-voltage portion including NMOS transistor (78) and PMOS transistor (82b) and a low-voltage portion including NMOS transistor (80) and PMOS transistor 82(a). The high-voltage NMOS transistor (78) includes... | 12/05/1995 |
| 5468666 | Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor 76 comprises a polysilicon gate 40 doped at a first dopant level. Low voltage NMOS transistor comprises a polysilicon gate 44 doped at a second d... | 11/21/1995 |
| 5467048 | Semiconductor device with two series-connected complementary misfets of same conduction type A low-voltage driven semiconductor device is simple to fabricate, operates at high speed, and consumes low power. The semiconductor device is made of first and second MISFETs connected in series. The MISFETs have channels of the same conduction type. If t... | 11/14/1995 |
| 5463347 | MOS uni-directional, differential voltage amplifier capable of amplifying signals having input common-mode voltage beneath voltage of lower supply and integrated circuit substrate An amplifier, preferably an integrated circuit, capable of accepting input common mode voltages below the circuit reference voltage or substrate voltage in the case of an integrated circuit. The amplifier comprises a differential voltage input having high... | 10/31/1995 |
| 5461259 | High-current integrated circuit Collective transistors in a high-current IC are arranged in the column and row directions on a substrate, with each row having two collective transistors. The collective transistors are connected in a multi-phase half bridge circuit by wiring conductors w... | 10/24/1995 |
| 5449936 | High current MOS transistor bridge structure A high current MOS transistor integrated bridge structure includes at least two arms, each having a first and a second MOS transistor. The structure is formed on an N++ substrate forming a positive potential output terminal, and an N-type epitaxial layer.... | 09/12/1995 |
| 5434531 | High voltage tolerant switch constructed for a low voltage CMOS process An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows ... | 07/18/1995 |
| 5432370 | High withstand voltage M I S field effect transistor and semiconductor integrated circuit A semiconductor integrated circuit device is provided in which a highly reliable and low cost intelligent power semiconductor is mounted on the same substrate as that of a control circuit having a logic element, such as a low withstand voltage CMOS etc., ... | 07/11/1995 |
| 5430313 | Transistor with an offset gate structure At the surface of a p-type silicon substrate, n-type source/drain diffused layers are formed. On the substrate between the source/drain diffused layers, a gate insulating film made of a silicon oxide film is formed so as to be isolated from the diffused l... | 07/04/1995 |
| 5420062 | Method of manufacturing an insulated gate FET having double-layered wells of low and high impurity concentrations This invention relates to an insulated gate FET in which the withstanding voltage and the latch-up resistant property are both made high. The structure thereof includes a second well formed in a first well and having an impurity concentration lower than t... | 05/30/1995 |
| 5414288 | Vertical transistor having an underlying gate electrode contact A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each forme... | 05/09/1995 |
| 5406096 | Device and method for high performance high voltage operation A high voltage device (10) having MOS input characteristics. A low voltage MOS transistor (12) is provided which has a source (18), a drain (22), and a gate (25). A high voltage transistor (14) is also provided which has a source (20), a drain (24), and g... | 04/11/1995 |
| 5403763 | Method of manufacturing a vertical channel FET A field effect transistor is formed on a side surface of an elevation protruded from the upper surface of a substrate. A gate electrode is formed on the side surface with a gate insulating film therebetween. Source and drain regions are formed in the top ... | 04/04/1995 |
| 5403769 | Process for producing a semiconductor device A process for producing a semiconductor device of the type having a semiconductor substrate; a semiconductor layer disposed on the semiconductor substrate; a first element formed in a region of the semiconductor layer and having a perimeter including a bo... | 04/04/1995 |
| 5401998 | Trench isolation using doped sidewalls A P-type substrate is immersed in a solution of potassium hydroxide (KOH) which etches exposed portions of the substrate to form trenches with sidewalls at an angle of 54.7 degrees with respect to the top surface of the substrate. A vertical boron implant... | 03/28/1995 |
| 5401987 | Self-cascoding CMOS device A self-cascoding transconductance circuit has cascoding and current sink/source FETs, serially connected with their gates tied together to receive an input voltage, wherein the cascoding FET has a threshold voltage having an absolute value at least 0.1 vo... | 03/28/1995 |
| 5399519 | Method of manufacturing semiconductor on insulator transistor with complementary transistor coupled to the channel The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabric... | 03/21/1995 |
| 5399916 | High-withstand-voltage integrated circuit In a high-withstand-voltage integrated circuit, several circuits are included at different potentials. Each circuit of a different potential has a power source, and interface circuits mediate signals between the circuits of different potentials. By this d... | 03/21/1995 |
| 5399514 | Method for manufacturing improved lightly doped diffusion (LDD) semiconductor device A semiconductor device comprises at least one p-type and n-type LDD transistors in a pair and a standard (non-LDD) transistor in the same substrate. Appropriate p-wells and n-wells are formed in the substrate, gate electrodes deposited, p-type and n-type ... | 03/21/1995 |
| 5399917 | High voltage tolerant switch constructed for a low voltage CMOS process An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows ... | 03/21/1995 |
| 5389810 | Semiconductor device having at least one symmetrical pair of MOSFETs A semiconductor device having at least one symmetrical pair of MOSFETs is provided. The device includes a semiconductor layer having an upper surface, an active region formed in the upper surface, an isolation region formed in the upper surface and enclos... | 02/14/1995 |
| 5371026 | Method for fabricating paired MOS transistors having a current-gain differential A semiconductor device (10) and process provides first and second, electrically coupled MOS transistors (14, 16) in which the current gain of the second MOS transistor (16) is greater than the current gain of the first MOS transistor (14). First and secon... | 12/06/1994 |
| 5346835 | Triple diffused lateral resurf insulated gate field effect transistor compatible with process and method A triple-diffused lateral RESURF transistor (55,57) uses a threshold voltage adjust implant (52, 54) in conjunction with a thinner gate oxide (64) to yield a device which is more compatible with CMOS VLSI manufacturing processes and which delivers better ... | 09/13/1994 |
| 5343099 | Output device capable of high speed operation and operating method thereof An output device is disclosed for restraining a ringing caused when the operation of a semiconductor integrated circuit device is speeded up. This output device includes first, second and third N channel transistors. The first N channel transistor has its... | 08/30/1994 |
| 5341013 | Semiconductor device provided with sense circuits A semiconductor device provided with a plurality of sense circuits, each sense circuit including a pair of MOS transistors such that their sources are commonly connected, and that the drain of one transistor and the gate of the other transistor are cross-... | 08/23/1994 |
| 5336915 | Semiconductor integrated circuit device having analog circuit and digital circuit formed on one chip First and second well regions of a second conductivity type are formed in a semiconductor substrate of a first conductivity type. An analog circuit is formed in the first well region. A digital circuit is formed in the second well region.... | 08/09/1994 |
| 5334871 | Field effect transistor signal switching device A field effect transistor signal switching device includes a semiconductor substrate including an active region; an input electrode disposed on the substrate and including a source electrode disposed on the active region and a source pad; first and second... | 08/02/1994 |
| 5332920 | Dielectrically isolated high and low voltage substrate regions A dielectric isolation substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wa... | 07/26/1994 |
| 5331192 | Semiconductor device A semiconductor device includes plural transistors in which the transistors themselves share a gate and a channel region and posses three or more source and drain regions. In such a configuration, a drain current is determined by the voltage application c... | 07/19/1994 |
| 5327000 | Semiconductor device interconnected to analog IC driven by high voltage In a MOS type LSI comprising an n channel-open-drain-transistor capable of connecting with an analog IC driven by a high voltage, a surge breakdown voltage and a drain breakdown voltage of the open-drain-transistor is increased, and hence the reliability ... | 07/05/1994 |
| 5324673 | Method of formation of vertical transistor A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each forme... | 06/28/1994 |
| 5319236 | Semiconductor device equipped with a high-voltage MISFET The invention provides a semiconductor device equipped with a high-voltage MISFET capable of forming a push-pull circuit on one chip by optimizing a junction-separation structure. In an n-channel MOSFET, when a potential is applied to the gate electrode, ... | 06/07/1994 |
| 5308782 | Semiconductor memory device and method of formation A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor sta... | 05/03/1994 |
| 5308778 | Method of formation of transistor and logic gates A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the c... | 05/03/1994 |
| 5306942 | Semiconductor device having a shield which is maintained at a reference potential A semiconductor layer is disposed on a semiconductor substrate and a first element is formed in a region of the semiconductor layer. A second element is formed in another region of the semiconductor layer. An insulating layer surrounds the perimeter of th... | 04/26/1994 |
| 5305257 | Semiconductor integrated circuit A semiconductor integrated circuit includes "n" cascaded inverters IVj ("j"="1" to "n") formed of MOS transistors. The size of an input side MOS transistor and the size of an output side MOS transistor of each inverter are determined so that an... | 04/19/1994 |
| 5302845 | Transistor with an offset gate structure At the surface of a p-type silicon substrate, n-type source/drain diffused layers are formed. On the substrate between the source/drain diffused layers, a gate insulating film made of a silicon oxide film is formed so as to be isolated from the diffused l... | 04/12/1994 |
