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| Number | Title | Issue Date |
| 7439590 | Semiconductor device A semiconductor device features connecting gate patterns of all transistors to a N+ or +P junction by the first connected wiring layer to prevent degradation of characteristics of the semiconductor device which results from plasma damages during a process. In order ... | 10/21/2008 |
| 7432554 | CMOS thin film transistor comprising common gate, logic device comprising the CMOS thin film transistor, and method of manufacturing the CMOS thin film transistor A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film tra... | 10/07/2008 |
| 7417269 | Magnetic impedance device, sensor apparatus using the same and method for manufacturing the same A magnetic sensor apparatus includes a semiconductor substrate and a magnetic impedance device for detecting a magnetic field. The magnetic impedance device is disposed on the substrate. The magnetic sensor apparatus has minimum size and is made with low manufacturi... | 08/26/2008 |
| 7413944 | CMOS image sensor and method of manufacturing the same In a CMOS image sensor manufacturing process, heavily doped p type impurity ions (for example, B) are implanted in a dummy moat region when the heavily doped p type impurity ions is implanted in a PMOS transistor region, so that metal ion contamination is removed. A... | 08/19/2008 |
| 7407828 | CMOS image sensor and manufacturing method thereof A gate insulation layer with a high dielectric constant for a CMOS image sensor formed by a damascene process. A silicide layer on a gate electrode layer is formed in both a pixel region and a peripheral circuit region, and a silicide layer on a source/drain region ... | 08/05/2008 |
| 7371650 | Method for producing a transistor structure A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and... | 05/13/2008 |
| 7361930 | Method for forming a multiple layer passivation film and a device incorporating the same A method of forming a multiple layer passivation film on a semiconductor device surface comprises placing a semiconductor device in a chemical vapor deposition reactor, introducing a nitrogen source into the reactor, introducing a carbon source into the reactor, dep... | 04/22/2008 |
| 7358545 | Bipolar junction transistor A bipolar junction transistor is provided. A p-type well region surrounds an n-type emitter and connects with the bottom of the emitter to serve as a base. A p-type base pick-up region connects with the base and surrounds the emitter. An n-type deep well, connected ... | 04/15/2008 |
| 7342289 | Strained silicon MOS devices A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a ... | 03/11/2008 |
| 7342284 | Semiconductor MOS transistor device and method for making the same A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and ... | 03/11/2008 |
| 7332433 | Methods of modulating the work functions of film layers Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where t... | 02/19/2008 |
| 7329940 | Semiconductor structure and method of manufacture A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which in... | 02/12/2008 |
| 7312500 | Manufacturing method of semiconductor device suppressing short-channel effect An ideal step-profile in a channel region is realized easily and reliably, whereby suppression of the short-channel effect and prevention of mobility degradation are achieved together. A silicon substrate is amorphized to a predetermined depth from a semiconductor f... | 12/25/2007 |
| 7309628 | Method of forming a semiconductor device A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding... | 12/18/2007 |
| 7285840 | Apparatus for confining inductively coupled surface currents A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and a... | 10/23/2007 |
| 7279725 | Vertical diode structures A method of making a vertical diode structure is provided, the vertical diode structure having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interio... | 10/09/2007 |
| 7279756 | Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof A process and apparatus for a semiconductor device is provided. A device comprises a first transistor having a first charge carrier type. The first transistor comprises a high-k gate dielectric and a first doped electrode. The first charge carrier type comprises one... | 10/09/2007 |
| 7271454 | Semiconductor memory device and method of manufacturing the same A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor ar... | 09/18/2007 |
| 7227229 | Active matrix display device comprising an inverter circuit The absolute value of the threshold voltage of a P-channel TFT is reduced by making its channel length shorter than that of an N-channel TFT by at least 20%, to thereby approximately equalize the threshold voltage absolute values of those TFTs. ... | 06/05/2007 |
| 7227240 | Semiconductor device with wire bond inductor and method A semiconductor device (10) includes a semiconductor die (20) and an inductor (30, 50) formed with a bonding wire (80) attached to a top surface (21) of the semiconductor die. The bonding wire is extended laterally a distance (L... | 06/05/2007 |
| 7227231 | Semiconductor integrated circuit device A semiconductor integrated circuit device has a first MOS transistor and a second MOS transistor. The first MOS transistor has a first source, a first gate electrode, and a first wiring metal connected to the first source and overlapping the first gate electrode. Th... | 06/05/2007 |
| 7217607 | Method for manufacturing semiconductor integrated circuit device In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is su... | 05/15/2007 |
| 7214975 | Semiconductor device with charge share countermeasure An aspect of the present invention provides a semiconductor device that includes a logic circuit including at least one transistor with a first channel type, a first transistor with a second channel type configured to provide the logic circuit with a first voltage a... | 05/08/2007 |
| 7211847 | CMOS image sensor A CMOS image sensor includes a photo sensing device for generating photo charges, a floating diffusion region for storing the photo charges generated by the photo sensing device therein, a transfer transistor connected between the photo sensing device and the floati... | 05/01/2007 |
| 7202535 | Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure. The manufacturing method comprises the steps of: providing a semiconductor substrate (1) having an upper su... | 04/10/2007 |
| 7170103 | Wafer with vertical diode structures A method of making a vertical diode is provided, the vertical diode having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the dio... | 01/30/2007 |
| 7118925 | Fabrication of a ferromagnetic inductor core and capacitor electrode in a single photo mask step A method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50a and a bottom portion of an induction coil 50a, forming an etch stop layer 250′, forming a f... | 10/10/2006 |
| 6879234 | Semiconductor integrated circuit Electrically conductive layers 1a and 2a connected to each other via a contact form one inductor, while electrically conductive layers 1b and 2b connected to each other via other contact form the other inductor... | 04/12/2005 |
| 6701607 | Integrated circuit inductors The invention relates to an inductor comprising a plurality of interconnected conductive segments interwoven with a substrate. The inductance of the inductor is increased through the use of coatings and films of ferromagnetic materials such as magnetic me... | 03/09/2004 |
| 6696898 | Differential crystal oscillator A periodic signal generation circuit includes a differential crystal oscillator suitable for integration on a semiconductor substrate. The oscillator utilizes an external crystal as a resonator. The circuit is designed such that differential sinusoidal si... | 02/24/2004 |
| 6696744 | Integrated circuit having a micromagnetic device and method of manufacture therefor A method of manufacturing an integrated circuit and an integrated circuit employing the same. In one embodiment, the method of manufacturing the integrated circuit includes (1) conformally mapping a micromagnetic device, including a ferromagnetic core, to... | 02/24/2004 |
| 6686825 | Chip inductor and manufacturing method therefor A chip inductor has electrode layers, insulating layers disposed on the electrode layers, and an uppermost insulating layer all disposed on a ceramic board. An inorganic pigment such as a Co oxide or an Al oxide is added to the insulating layer at a conce... | 02/03/2004 |
| 6680518 | Monolithic inductance-enhancing integrated circuits, complementary metal oxide semiconductor (CMOS) inductance-enhancing integrated circuits, inductor assemblies, and inductance-multiplying methods Monolithic inductance-enhancing integrated circuits, complementary metal oxide semiconductor (CMOS) inductance-enhancing integrated circuits, inductor assemblies, and inductance-multiplying methods are described. In one embodiment, a monolithic inductance... | 01/20/2004 |
| 6667217 | Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step,... | 12/23/2003 |
| 6661068 | Semiconductor device and method of providing regions of low substrate capacitance A semiconductor structure (1), comprising a isolation region (5) formed on a semiconductor material (10). A pillar (15) is formed in the semiconductor material under the isolation region, where the pillar is capped with a first dielectric material (20) to... | 12/09/2003 |
| 6661078 | Inductance element and semiconductor device The inductance element according to the present invention includes: an inductance section, provided above a semiconductor substrate via insulating films, which is composed of a conductive film pattern setted to have a predetermined inductance value; and a... | 12/09/2003 |
| 6661079 | Semiconductor-based spiral capacitor Increased capacitance per unit of area with reduced series resistance and inductance is provided by a semiconductor-based capacitor with a spiral shape. The capacitor utilizes a plurality of patterned metal layers that each have a first trace with a spira... | 12/09/2003 |
| 6657310 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or pol... | 12/02/2003 |
| 6655964 | Low cost integrated out-of-plane micro-device structures and method of making Several methods and structures for improving the yield of out-of-plane micro-device structures including springs and coils are described. In one method the elastic members have graded perforations for controlling rate of release. In another method and str... | 12/02/2003 |
| 6656813 | Low loss high Q inductor A high Q inductive element with low losses, high inductance and high efficiency is disclosed. The high Q inductive element with one or more inductive loops is formed over a silicon micro structure with thin support elements formed by deep plasma etching i... | 12/02/2003 |
